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proper printing of the pipe_int tx_pipe

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Priec
2025-11-18 22:56:28 +01:00
parent 45df1e87e4
commit 516309aed2
2 changed files with 10 additions and 13 deletions
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8
semestralka_1d_rx_bez_dma/Cargo.lock generated
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@@ -1064,17 +1064,17 @@ dependencies = [
[[package]] [[package]]
name = "stm32-fmc" name = "stm32-fmc"
version = "0.4.0" version = "0.3.2"
source = "registry+https://github.com/rust-lang/crates.io-index" source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "72692594faa67f052e5e06dd34460951c21e83bc55de4feb8d2666e2f15480a2" checksum = "c7f0639399e2307c2446c54d91d4f1596343a1e1d5cab605b9cce11d0ab3858c"
dependencies = [ dependencies = [
"embedded-hal 1.0.0", "embedded-hal 0.2.7",
] ]
[[package]] [[package]]
name = "stm32-metapac" name = "stm32-metapac"
version = "18.0.0" version = "18.0.0"
source = "git+https://github.com/embassy-rs/stm32-data-generated?tag=stm32-data-22374e3344a2c9150b9b3d4da45c03f398fdc54e#31546499ddabe97044beae13ca8b535575b52a56" source = "git+https://github.com/embassy-rs/stm32-data-generated?tag=stm32-data-b9f6b0c542d85ee695d71c35ced195e0cef51ac0#9b8fb67703361e2237b6c1ec4f1ee5949223d412"
dependencies = [ dependencies = [
"cortex-m", "cortex-m",
"cortex-m-rt", "cortex-m-rt",

13
semestralka_1d_rx_bez_dma/src/bin/main.rs
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@@ -121,10 +121,7 @@ async fn main(spawner: Spawner) {
while !tim6_regs.sr().read().uif() { while !tim6_regs.sr().read().uif() {
yield_now().await; yield_now().await;
} }
// Clear interrupt flag
tim6_regs.sr().modify(|w| w.set_uif(false)); tim6_regs.sr().modify(|w| w.set_uif(false));
// Sample PD6 level
let bit = rx_pin.is_high(); let bit = rx_pin.is_high();
levels[idx] = bit as u8; levels[idx] = bit as u8;
idx += 1; idx += 1;
@@ -138,10 +135,10 @@ async fn main(spawner: Spawner) {
idx = 0; idx = 0;
} }
let n1 = PIPE_INT_TX.read(&mut buf).await; // let n1 = PIPE_INT_TX.read(&mut buf).await;
if n1 > 0 { // if n1 > 0 {
info!("PIPE_INT_TX received: {:a}", &buf[..n1]); // info!("PIPE_INT_TX received: {:a}", &buf[..n1]);
} // }
Timer::after(Duration::from_millis(1)).await; Timer::after(Duration::from_millis(1)).await;
yield_now().await; yield_now().await;
@@ -174,7 +171,7 @@ pub async fn bridge_usart2_rx_to_usart1_tx(
let n = usart2_rx.read(&mut buf).await; let n = usart2_rx.read(&mut buf).await;
if n > 0 { if n > 0 {
let _ = usart1_tx.write(&buf[..n]).await; let _ = usart1_tx.write(&buf[..n]).await;
// info!("bridge: USART2 -> USART1 sent {} bytes", n); info!("Buffer USART2 -> USART1 bytes: {:?}", &buf[..n]);
} }
yield_now().await; yield_now().await;
} }