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proper printing of the pipe_int tx_pipe

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Priec
2025-11-18 22:56:28 +01:00
parent 45df1e87e4
commit 516309aed2
2 changed files with 10 additions and 13 deletions
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15
semestralka_1d_rx_bez_dma/src/bin/main.rs
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@@ -121,10 +121,7 @@ async fn main(spawner: Spawner) {
while !tim6_regs.sr().read().uif() {
yield_now().await;
}
// Clear interrupt flag
tim6_regs.sr().modify(|w| w.set_uif(false));
// Sample PD6 level
let bit = rx_pin.is_high();
levels[idx] = bit as u8;
idx += 1;
@@ -138,11 +135,11 @@ async fn main(spawner: Spawner) {
idx = 0;
}
let n1 = PIPE_INT_TX.read(&mut buf).await;
if n1 > 0 {
info!("PIPE_INT_TX received: {:a}", &buf[..n1]);
}
// let n1 = PIPE_INT_TX.read(&mut buf).await;
// if n1 > 0 {
// info!("PIPE_INT_TX received: {:a}", &buf[..n1]);
// }
Timer::after(Duration::from_millis(1)).await;
yield_now().await;
}
@@ -174,7 +171,7 @@ pub async fn bridge_usart2_rx_to_usart1_tx(
let n = usart2_rx.read(&mut buf).await;
if n > 0 {
let _ = usart1_tx.write(&buf[..n]).await;
// info!("bridge: USART2 -> USART1 sent {} bytes", n);
info!("Buffer USART2 -> USART1 bytes: {:?}", &buf[..n]);
}
yield_now().await;
}