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Filipriec
2025-11-04 22:00:34 +01:00
parent 92e27ad076
commit 44f154e289
1 changed files with 2 additions and 1 deletions
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3
dma_gpio/src/bin/main.rs
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@@ -61,7 +61,7 @@ async fn main(spawner: Spawner) {
tx_opts.half_transfer_ir = true; tx_opts.half_transfer_ir = true;
tx_opts.complete_transfer_ir = true; tx_opts.complete_transfer_ir = true;
// SAFETY: tx_ring_mem is exclusive, bsrr_ptr points to GPIOA BSRR, paced by TIM6. // SAFETY: tx_ring_mem is exclusive
let mut tx_ring = unsafe { let mut tx_ring = unsafe {
WritableRingBuffer::new( WritableRingBuffer::new(
p.GPDMA1_CH0, p.GPDMA1_CH0,
@@ -71,6 +71,7 @@ async fn main(spawner: Spawner) {
tx_opts, tx_opts,
) )
}; };
// Start DMA
tx_ring.start(); tx_ring.start();
info!("TX DMA ring started"); info!("TX DMA ring started");