only improvements

This commit is contained in:
Priec
2025-11-05 14:45:36 +01:00
parent d57d16935d
commit 41c31f6b2a
4 changed files with 18 additions and 15 deletions

View File

@@ -6,7 +6,7 @@ use embassy_stm32::{
Peri,
};
use embassy_stm32::dma::{
ReadableRingBuffer as DmaRingRx,
ReadableRingBuffer,
TransferOptions,
};
use crate::config::{RX_OVERSAMPLE, UART_CFG};
@@ -30,7 +30,7 @@ pub async fn rx_dma_task(
opts.complete_transfer_ir = true;
// SAFETY: ring is exclusive to this task
let mut rx = unsafe { DmaRingRx::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
rx.start();
let mut chunk = [0u8; 256];

View File

@@ -1,7 +1,8 @@
// src/software_uart/gpio_dma_uart_tx.rs
use embassy_stm32::dma::Request;
use embassy_stm32::dma::WritableRingBuffer;
use crate::software_uart::uart_emulation::{UartConfig, encode_uart_byte_cfg};
use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
use crate::config::UART_CFG;
// kapitola 17.4.11 - 2 casovace pre 2 DMA
pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
@@ -11,11 +12,10 @@ pub async fn write_uart_frames_to_ring(
ring: &mut WritableRingBuffer<'static, u32>,
pin_bit: u8,
bytes: &[u8],
cfg: &UartConfig,
) {
for &b in bytes {
let mut frame = [0u32; 12];
let used = encode_uart_byte_cfg(pin_bit, b, cfg, &mut frame);
let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
// Will wait until all words are written
ring.write_exact(&frame[..used]).await.unwrap();

View File

@@ -40,7 +40,8 @@ pub fn encode_uart_byte_cfg(
) -> usize {
// GPIOx_BSRR register str. 636 kap. 13.4.7
let set_high = |bit: u8| -> u32 { 1u32 << bit };
let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
let set_low = |bit: u8| -> u32 { 0 };
// let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
let mut idx = 0usize;