timing uml diagrams added

semestralka_1_final_crate/software_uart/docs/decode_uml.txt

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+@startuml
+scale 5 as 100 pixels
+
+clock "TIM7" as clk with period 1
+binary "UART RX" as uart
+binary "Sample" as smp
+
+@0
+uart is low
+smp is low
+
+@8
+smp is high
+
+@9
+smp is low
+
+@16
+uart is high
+
+@24
+smp is high
+
+@25
+smp is low
+
+@32
+uart is high
+@enduml

semestralka_1_final_crate/software_uart/docs/encode_uml.txt

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+@startuml
+scale 5 as 100 pixels
+
+clock "TIM6" as clk with period 1
+binary "GPIO TX" as gpio
+binary "BSRR write" as bsrr
+
+@0
+gpio is low
+bsrr is high
+
+@1
+bsrr is low
+
+@16
+gpio is high
+bsrr is high
+
+@17
+bsrr is low
+
+@32
+gpio is high
+@enduml