From 3e2ad6eb7d591c257f41a86e2b06de3533d98fff Mon Sep 17 00:00:00 2001
From: Filipriec <filippriec@gmail.com>
Date: Mon, 24 Nov 2025 09:41:46 +0100
Subject: [PATCH] timing uml diagrams added

---
 .../software_uart/docs/decode_uml.txt         | 29 +++++++++++++++++++
 .../software_uart/docs/encode_uml.txt         | 24 +++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 semestralka_1_final_crate/software_uart/docs/decode_uml.txt
 create mode 100644 semestralka_1_final_crate/software_uart/docs/encode_uml.txt

diff --git a/semestralka_1_final_crate/software_uart/docs/decode_uml.txt b/semestralka_1_final_crate/software_uart/docs/decode_uml.txt
new file mode 100644
index 0000000..d77ef87
--- /dev/null
+++ b/semestralka_1_final_crate/software_uart/docs/decode_uml.txt
@@ -0,0 +1,29 @@
+@startuml
+scale 5 as 100 pixels
+
+clock "TIM7" as clk with period 1
+binary "UART RX" as uart
+binary "Sample" as smp
+
+@0
+uart is low
+smp is low
+
+@8
+smp is high
+
+@9
+smp is low
+
+@16
+uart is high
+
+@24
+smp is high
+
+@25
+smp is low
+
+@32
+uart is high
+@enduml
diff --git a/semestralka_1_final_crate/software_uart/docs/encode_uml.txt b/semestralka_1_final_crate/software_uart/docs/encode_uml.txt
new file mode 100644
index 0000000..f90bd40
--- /dev/null
+++ b/semestralka_1_final_crate/software_uart/docs/encode_uml.txt
@@ -0,0 +1,24 @@
+@startuml
+scale 5 as 100 pixels
+
+clock "TIM6" as clk with period 1
+binary "GPIO TX" as gpio
+binary "BSRR write" as bsrr
+
+@0
+gpio is low
+bsrr is high
+
+@1
+bsrr is low
+
+@16
+gpio is high
+bsrr is high
+
+@17
+bsrr is low
+
+@32
+gpio is high
+@enduml