working at the baud rate 600

semestralka_1e_tx_bez_dma/src/bin/main.rs

@@ -100,20 +100,14 @@ async fn main(spawner: Spawner) {
 
         counter += 1;
         let msg = if counter % 2 == 0 {
-            b"AAAAA\n"
+            b"AAAAA\r\n"
         } else {
-            b"Hello\n"
+            b"Hello\r\n"
         };
         PIPE_SW_TX.write(msg).await;
         info!("Sent: {:a}", msg);
 
-        Timer::after(Duration::from_millis(100)).await;
-        
-        // Also read any incoming data from internal UART RX pipe
-        let n2 = PIPE_INT_RX.read(&mut buf).await;
-        if n2 > 0 {
-            info!("HW INT UART RX pipe: {:a}", &buf[..n2]);
-        }
+        Timer::after(Duration::from_secs(3)).await;
 
         yield_now().await;
     }
@@ -156,6 +150,7 @@ pub async fn tx_cpu_task(
 ) {
     use dma_gpio::software_uart::uart_emulation::encode_uart_byte_cfg;
     use embassy_futures::yield_now;
+    use dma_gpio::config::{TX_PIN_BIT, UART_CFG};
 
     // Access TIM6 registers directly via PAC
     let tim6_regs = embassy_stm32::pac::TIM6;
@@ -171,11 +166,24 @@ pub async fn tx_cpu_task(
 
         for &byte in &rx_buf[..n] {
             let used = encode_uart_byte_cfg(TX_PIN_BIT, byte, &UART_CFG, &mut frame_buf);
+
+            // === SYNC LOGIC ===
+            // Reset timer counter to 0 using Event Generation Register (UG bit)
+            // This ensures we start counting exactly from now.
+            tim6_regs.egr().write(|w| w.set_ug(true));
+            // The UG event sets the UIF flag immediately. We must clear it.
+            tim6_regs.sr().write(|w| w.set_uif(false));
+
+            // Now we loop through the encoded frame.
+            // Since we just reset the timer and cleared UIF, the first wait
+            // will block for exactly 1 bit-period.
+            // This effectively adds 1 bit of idle time before the Start Bit,
+            // which guarantees the line is stable High before dropping Low.
             for word in &frame_buf[..used] {
                 while !tim6_regs.sr().read().uif() {
                     yield_now().await;
                 }
-                tim6_regs.sr().modify(|w| w.set_uif(false));
+                tim6_regs.sr().write(|w| w.set_uif(false));
                 unsafe { core::ptr::write_volatile(bsrr_ptr, *word) };
             }
         }

semestralka_1e_tx_bez_dma/src/config.rs

@@ -3,7 +3,7 @@ use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::pipe::Pipe;
 
-pub const BAUD: u32 = 115_200;
+pub const BAUD: u32 = 600;
 // pub const TX_PIN_BIT: u8 = 2; // PA2
 // pub const RX_PIN_BIT: u8 = 3; // PA3
 pub const TX_PIN_BIT: u8 = 0; // PB2