there is some bug

This commit is contained in:
Priec
2025-11-12 16:07:59 +01:00
parent 829cff872f
commit 05662a45d0
9 changed files with 120 additions and 29 deletions

View File

@@ -73,9 +73,9 @@ async fn main(spawner: Spawner) {
spawner.spawn(rx_dma_task(p.GPDMA1_CH1, sw_rx_ring, &PIPE_SW_RX).unwrap());
// Create and start the TX DMA ring in main.
// let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
spawner.spawn(tx_dma_task(p.GPDMA1_CH0, odr_ptr, sw_tx_ring, &PIPE_SW_TX).unwrap());
let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
// let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32; // NEEDS DECODE CHANGE
spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, sw_tx_ring, &PIPE_SW_TX).unwrap());
// EDN OF SOFTWARE UART
@@ -95,11 +95,10 @@ async fn main(spawner: Spawner) {
let n1 = PIPE_HW_RX.read(&mut buf).await;
if n1 > 0 {
info!("PC received: {:a}", &buf[..n1]);
}
if n1 > 0 {
let _ = PIPE_SW_TX.write(&buf[..n1]).await;
info!("SW UART TX sent echo: {:a}", &buf[..n1]);
}
yield_now().await;
let n2 = PIPE_SW_RX.read(&mut buf).await;
if n2 > 0 {

View File

@@ -3,8 +3,9 @@ use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
pub const BAUD: u32 = 115_200;
pub const BAUD: u32 = 9_600;
pub const TX_PIN_BIT: u8 = 2; // PA2
pub const RX_PIN_BIT: u8 = 3; // PA3
pub const TX_OVERSAMPLE: u16 = 1;
pub const RX_OVERSAMPLE: u16 = 16;

View File

@@ -5,6 +5,7 @@ use embassy_stm32::{
peripherals::GPDMA1_CH1,
Peri,
};
use crate::config::RX_PIN_BIT;
use embassy_stm32::dma::{
ReadableRingBuffer,
TransferOptions,
@@ -13,6 +14,7 @@ use crate::config::{RX_OVERSAMPLE, UART_CFG};
use crate::software_uart::decode_uart_samples;
use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
use embassy_futures::yield_now;
use defmt::info;
// datasheet tabulka 137
pub const TIM7_UP_REQ: Request = 5;
@@ -34,10 +36,25 @@ pub async fn rx_dma_task(
let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
rx.start();
let mut chunk = [0u8; 256];
let mut raw_chunk = [0u8; 256];
let mut levels = [0u8; 256];
loop {
let _ = rx.read_exact(&mut chunk).await;
let decoded = decode_uart_samples(&chunk, RX_OVERSAMPLE, &UART_CFG);
info!("rx_dma_task waiting for DMA data...");
let _ = rx.read_exact(&mut raw_chunk).await;
for (i, b) in raw_chunk.iter().enumerate() {
levels[i] = ((*b >> RX_PIN_BIT) & 1) as u8;
}
let decoded = decode_uart_samples(&levels, RX_OVERSAMPLE, &UART_CFG);
if !decoded.is_empty() {
info!("SW RX raw samples (first 32): {:a}", &levels[..32]);
info!(
"SW RX decoded {} bytes: {:a}",
decoded.len(),
decoded.as_slice()
);
}
pipe_rx.write(&decoded).await;
yield_now().await;
}

View File

@@ -42,7 +42,7 @@ pub async fn encode_uart_frames<'a>(
#[task]
pub async fn tx_dma_task(
ch: Peri<'static, GPDMA1_CH0>,
odr_ptr: *mut u32,
register: *mut u32, // Either odr or bsrr
tx_ring_mem: &'static mut [u32],
pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
) {
@@ -55,7 +55,7 @@ pub async fn tx_dma_task(
WritableRingBuffer::new(
ch,
TIM6_UP_REQ,
odr_ptr,
register,
tx_ring_mem,
tx_opts,
)
@@ -78,6 +78,7 @@ pub async fn tx_dma_task(
if used > 0 {
let _ = tx_ring.write_exact(&frame_buf[..used]).await;
}
info!("tx_dma_task wrote {} words", used);
yield_now().await;
}
}

View File

@@ -40,8 +40,8 @@ pub fn encode_uart_byte_cfg(
) -> usize {
// GPIOx_BSRR register str. 636 kap. 13.4.7
let set_high = |bit: u8| -> u32 { 1u32 << bit };
let set_low = |bit: u8| -> u32 { 0 };
// let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
// let set_low = |bit: u8| -> u32 { 0 }; // ODR
let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
let mut idx = 0usize;