237 lines
8.2 KiB
VHDL
237 lines
8.2 KiB
VHDL
-- top_modul.vhd
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity top_modul is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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START : in STD_LOGIC;
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SW_MODE : in STD_LOGIC; -- '0' = HH:MM, '1' = MM:SS
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SW_ALARM_SET : in STD_LOGIC; -- '0' = Display Clock, '1' = Set Alarm
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SW_STOP_SET : in STD_LOGIC; -- '0' = Display Clock, '1' = Set Stopky
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SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
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BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
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RST_B : in STD_LOGIC;
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RST_C : in STD_LOGIC;
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SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
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ANODS : out STD_LOGIC_VECTOR (3 downto 0);
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ALARM_LED : out STD_LOGIC -- LED lights up when alarm triggers
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);
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end top_modul;
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architecture Behavioral of top_modul is
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component divider is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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CLK_1_Hz : out STD_LOGIC); -- Enable pulse
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end component;
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component divider_400Hz is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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CLK_400_Hz : out STD_LOGIC); -- Enable pulse
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end component;
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signal clk_1_Hz : std_logic;
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signal clk_400_Hz : std_logic;
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signal s_ce_units : std_logic;
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-- Top_modul can carry data between the two submodules thanks to this
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signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0);
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signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0);
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signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0);
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-- Alarm display clock
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signal alrm_s_units, alrm_s_tens : std_logic_vector(3 downto 0);
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signal alrm_m_units, alrm_m_tens : std_logic_vector(3 downto 0);
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signal alrm_h_units, alrm_h_tens : std_logic_vector(3 downto 0);
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-- stopky clock
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signal stop_s_units, stop_s_tens : std_logic_vector(3 downto 0);
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signal stop_m_units, stop_m_tens : std_logic_vector(3 downto 0);
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signal stop_h_units, stop_h_tens : std_logic_vector(3 downto 0);
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-- cap stopky clock
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signal cap_s_units, cap_s_tens : std_logic_vector(3 downto 0);
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signal cap_m_units, cap_m_tens : std_logic_vector(3 downto 0);
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signal cap_h_units, cap_h_tens : std_logic_vector(3 downto 0);
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-- Signals to send to the display
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signal d0, d1, d2, d3 : std_logic_vector(3 downto 0);
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signal load_clock : std_logic_vector(3 downto 0);
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signal load_alarm : std_logic_vector(3 downto 0);
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signal load_stopky : std_logic_vector(3 downto 0);
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-- stopky ci behaju
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signal stops_running : std_logic := '0';
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signal stops_reset: std_logic := '0';
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signal sw_stop_prev : std_logic := '0';
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begin
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U_DIV_1HZ : divider
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port map (
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CLK => CLK,
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RST => RST,
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CLK_1_Hz => clk_1_Hz
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);
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U_DIV_REFRESH : divider_400Hz
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port map (
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CLK => CLK,
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RST => RST,
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CLK_400_Hz => clk_400_Hz
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);
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s_ce_units <= clk_1_Hz and START;
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load_clock <= BTN_LOAD when SW_ALARM_SET = '0' else "0000";
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load_alarm <= BTN_LOAD when SW_ALARM_SET = '1' else "0000";
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-- Clock Engine submodule
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U_CLOCK_CORE : entity work.clock_logic
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port map (
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CLK => CLK,
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RST => RST,
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CE_1HZ => s_ce_units,
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SW_DIN => SW_DIN,
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BTN_LOAD => load_clock,
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S_UNITS => sig_s_units,
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S_TENS => sig_s_tens,
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M_UNITS => sig_m_units,
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M_TENS => sig_m_tens,
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H_UNITS => sig_h_units,
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H_TENS => sig_h_tens
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);
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-- Clock Engine submodule for alarm
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U_ALARM_CORE : entity work.clock_logic
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port map (
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CLK => CLK,
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RST => RST,
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CE_1HZ => '0',
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SW_DIN => SW_DIN,
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BTN_LOAD => load_alarm,
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S_UNITS => alrm_s_units,
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S_TENS => alrm_s_tens,
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M_UNITS => alrm_m_units,
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M_TENS => alrm_m_tens,
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H_UNITS => alrm_h_units,
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H_TENS => alrm_h_tens
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);
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stops_running <= s_ce_units;
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stops_reset <= RST or RST_C;
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-- Clock Engine submodule for stopky
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U_STOPKY_CORE : entity work.clock_logic
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port map (
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CLK => CLK,
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RST => stops_reset,
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CE_1HZ => stops_running,
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SW_DIN => "0000",
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BTN_LOAD => "0000",
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S_UNITS => stop_s_units,
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S_TENS => stop_s_tens,
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M_UNITS => stop_m_units,
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M_TENS => stop_m_tens,
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H_UNITS => stop_h_units,
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H_TENS => stop_h_tens
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);
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-- Comparator Logic for alarm LED to be ON or OFF
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-- TODO BUG proste niekedy na zaciatku ledka svieti aj ked ma byt zhasnuta
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process(CLK)
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begin
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if rising_edge(CLK) then
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sw_stop_prev <= SW_STOP_SET;
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-- alarm
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if RST = '1' or RST_B = '1' then
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ALARM_LED <= '0';
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-- Match condition (HH:MM)
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elsif (START = '1' and
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sig_h_tens = alrm_h_tens and sig_h_units = alrm_h_units and
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sig_m_tens = alrm_m_tens and sig_m_units = alrm_m_units and
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sig_s_tens = "0000" and sig_s_units = "0000") then
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ALARM_LED <= '1';
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end if;
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if RST = '1' or RST_C = '1' then
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cap_s_units <= "0000";
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cap_s_tens <= "0000";
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cap_m_units <= "0000";
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cap_m_tens <= "0000";
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cap_h_units <= "0000";
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cap_h_tens <= "0000";
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stops_running <= '0';
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elsif SW_STOP_SET = '1' and sw_stop_prev = '0' then
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cap_s_units <= stop_s_units;
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cap_s_tens <= stop_s_tens;
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cap_m_units <= stop_m_units;
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cap_m_tens <= stop_m_tens;
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cap_h_units <= stop_h_units;
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cap_h_tens <= stop_h_tens;
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end if;
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end if;
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end process;
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-- -- Mode Multiplexing
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-- -- If SW_MODE = '1', show MM:SS. If '0', show HH:MM.
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-- d0 <= sig_s_units when SW_MODE = '1' else sig_m_units;
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-- d1 <= sig_s_tens when SW_MODE = '1' else sig_m_tens;
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-- d2 <= sig_m_units when SW_MODE = '1' else sig_h_units;
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-- d3 <= sig_m_tens when SW_MODE = '1' else sig_h_tens;
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-- Mode Multiplexing (4 digit display)
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process(SW_ALARM_SET, SW_MODE,
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sig_s_units, sig_s_tens, sig_m_units, sig_m_tens, sig_h_units, sig_h_tens,
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alrm_m_units, alrm_m_tens, alrm_h_units, alrm_h_tens, stop_s_units, stop_s_tens,
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stop_m_units, stop_m_tens, stop_h_units, stop_h_tens )
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begin
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if SW_ALARM_SET = '1' then
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-- While setting alarm, always show Alarm HH:MM
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d0 <= alrm_m_units;
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d1 <= alrm_m_tens;
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d2 <= alrm_h_units;
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d3 <= alrm_h_tens;
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elsif SW_STOP_SET = '1' then
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if SW_MODE = '1' then
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-- Stopky (MM:SS)
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d0 <= cap_s_units;
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d1 <= cap_s_tens;
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d2 <= cap_m_units;
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d3 <= cap_m_tens;
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else
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-- Stopky (HH:MM)
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d0 <= cap_m_units;
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d1 <= cap_m_tens;
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d2 <= cap_h_units;
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d3 <= cap_h_tens;
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end if;
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else
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-- Normal Operation
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if SW_MODE = '1' then
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-- Show Seconds and Minutes (MM:SS)
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d0 <= sig_s_units;
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d1 <= sig_s_tens;
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d2 <= sig_m_units;
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d3 <= sig_m_tens;
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else
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-- Show Minutes and Hours (HH:MM)
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d0 <= sig_m_units;
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d1 <= sig_m_tens;
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d2 <= sig_h_units;
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d3 <= sig_h_tens;
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end if;
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end if;
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end process;
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U_DISPLAY : entity work.display_driver
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port map (
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CLK => clk_400_Hz,
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RST => RST,
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DIGIT_0 => d0,
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DIGIT_1 => d1,
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DIGIT_2 => d2,
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DIGIT_3 => d3,
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SEGMENTS => SEGMENTS,
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ANODES => ANODS
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);
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end Behavioral;
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