51 lines
1.2 KiB
VHDL
51 lines
1.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09.03.2026 15:39:11
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-- Design Name:
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-- Module Name: decoder_bottom - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity decoder_an is
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Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
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ANODES : in STD_LOGIC_VECTOR (3 downto 0));
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end decoder_an;
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architecture Behavioral of decoder_an is
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begin
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with SEL select
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ANODES <= "1000" when "00",
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"0100" when "01",
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"0010" when "10",
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"0001" when "11",
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"0000" when others;
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end Behavioral;
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