79 lines
1.9 KiB
VHDL
79 lines
1.9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 23.02.2026 13:09:41
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-- Design Name:
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-- Module Name: top_model - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity top_model is
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Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);
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ANODS : out STD_LOGIC_VECTOR (3 downto 0);
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SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0));
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end top_model;
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architecture Behavioral of top_model is
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begin
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--HEX-to-seven-segment decoder
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-- HEX: in STD_LOGIC_VECTOR (3 downto 0);
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-- LED: out STD_LOGIC_VECTOR (6 downto 0);
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--
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-- segment encoinputg
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-- 0
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-- ---
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-- 5 | | 1
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-- --- <- 6
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-- 4 | | 2
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-- ---
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-- 3
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with SW SELect
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SEGMENTS <= "01111001" when "0001", --1
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"00100100" when "0010", --2
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"00110000" when "0011", --3
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"00011001" when "0100", --4
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"00010010" when "0101", --5
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"00000010" when "0110", --6
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"01111000" when "0111", --7
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"00000000" when "1000", --8
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"00010000" when "1001", --9
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"00001000" when "1010", --A
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"00000011" when "1011", --b
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"01000110" when "1100", --C
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"00100001" when "1101", --d
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"00000110" when "1110", --E
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"00001110" when "1111", --F
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"01000000" when others; --0
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ANODS <= "1110";
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end Behavioral;
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