85 lines
2.0 KiB
VHDL
85 lines
2.0 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 02.03.2026 12:53:10
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-- Design Name:
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-- Module Name: top_modul_test - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity top_modul_test is
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Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);
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ANODS : out STD_LOGIC_VECTOR (3 downto 0);
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SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0));
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end top_modul_test;
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architecture Behavioral of top_modul_test is
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component top_modul_test is
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Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);
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ANODS : out STD_LOGIC_VECTOR (3 downto 0);
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SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0));
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end component;
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constant TIME_DELTA : time := 10ns;
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signal SW_tb : STD_LOGIC_VECTOR (3 downto 0);
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signal ANODS_tb : STD_LOGIC_VECTOR (3 downto 0);
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signal SEGMENTS_tb : STD_LOGIC_VECTOR (7 downto 0);
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begin
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top_modul_inst_0: top_modul_test
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port map ( SW => SW_tb,
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ANODS => ANODS_tb,
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SEGMENTS => SEGMENTS_tb
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);
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simulation: process
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begin
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SW_tb <= "0000";
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ANODS_tb <= "0001";
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wait for TIME_DELTA;
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SW_tb <= "0000";
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wait for TIME_DELTA;
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SW_tb <= "0001";
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wait for TIME_DELTA;
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SW_tb <= "0010";
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wait for TIME_DELTA;
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SW_tb <= "0011";
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wait for TIME_DELTA;
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SW_tb <= "0111";
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wait for TIME_DELTA;
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SW_tb <= "0101";
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wait for TIME_DELTA;
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SW_tb <= "1111";
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wait;
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end process;
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end Behavioral;
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