61 lines
1.5 KiB
VHDL
61 lines
1.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09.03.2026 14:43:21
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-- Design Name:
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-- Module Name: divider - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity divider is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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CLK_1_Hz : out STD_LOGIC);
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end divider;
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architecture Behavioral of divider is
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-- 27 bits is enough for 100 million
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signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0');
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begin
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process(CLK)
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begin
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if rising_edge(CLK) then
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if RST = '1' then
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s_cnt <= (others => '0');
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CLK_1_Hz <= '0';
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elsif s_cnt = 99_999_999 then
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s_cnt <= (others => '0');
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CLK_1_Hz <= '1'; -- The pulse
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else
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s_cnt <= s_cnt + 1;
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CLK_1_Hz <= '0';
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end if;
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end if;
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end process;
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end Behavioral;
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