65 lines
2.0 KiB
VHDL
65 lines
2.0 KiB
VHDL
-- display_drive.vhd
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity display_driver is
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Port (
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CLK : in STD_LOGIC; -- Connect to 400Hz signal
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RST : in STD_LOGIC;
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-- The four BCD digits from your counters
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DIGIT_0 : in STD_LOGIC_VECTOR (3 downto 0);
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DIGIT_1 : in STD_LOGIC_VECTOR (3 downto 0);
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DIGIT_2 : in STD_LOGIC_VECTOR (3 downto 0);
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DIGIT_3 : in STD_LOGIC_VECTOR (3 downto 0);
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-- Physical outputs to the FPGA pins
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SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
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ANODES : out STD_LOGIC_VECTOR (3 downto 0)
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);
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end display_driver;
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architecture Behavioral of display_driver is
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component counter_2bit is
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Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC;
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COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
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end component;
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component decoder_an is
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Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
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ANODES : out STD_LOGIC_VECTOR (3 downto 0));
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end component;
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component mux is
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Port ( I0, I1, I2, I3 : in STD_LOGIC_VECTOR (3 downto 0);
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S : in STD_LOGIC_VECTOR (1 downto 0);
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Y : out STD_LOGIC_VECTOR (3 downto 0));
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end component;
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component dec_seg is
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Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
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seg : out STD_LOGIC_VECTOR (7 downto 0));
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end component;
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-- Internal signals stay here now
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signal s_cnt_2bit : std_logic_vector(1 downto 0);
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signal s_mux_out : std_logic_vector(3 downto 0);
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begin
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U_CNT_2BIT : counter_2bit
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port map (CLK => CLK, RST => RST, COUNT_OUT => s_cnt_2bit);
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U_DEC_ANODES : decoder_an
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port map (SEL => s_cnt_2bit, ANODES => ANODES);
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U_MUX : mux
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port map (I0 => DIGIT_0, I1 => DIGIT_1, I2 => DIGIT_2, I3 => DIGIT_3,
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S => s_cnt_2bit, Y => s_mux_out);
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U_DEC_SEG : dec_seg
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port map (BCD => s_mux_out, SEG => SEGMENTS);
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end Behavioral;
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