56 lines
1.3 KiB
VHDL
56 lines
1.3 KiB
VHDL
----------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 09.03.2026 15:32:13
|
|
-- Design Name:
|
|
-- Module Name: counter_2bit - Behavioral
|
|
-- Project Name:
|
|
-- Target Devices:
|
|
-- Tool Versions:
|
|
-- Description:
|
|
--
|
|
-- Dependencies:
|
|
--
|
|
-- Revision:
|
|
-- Revision 0.01 - File Created
|
|
-- Additional Comments:
|
|
--
|
|
----------------------------------------------------------------------------------
|
|
|
|
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
|
|
|
-- Uncomment the following library declaration if using
|
|
-- arithmetic functions with Signed or Unsigned values
|
|
--use IEEE.NUMERIC_STD.ALL;
|
|
|
|
-- Uncomment the following library declaration if instantiating
|
|
-- any Xilinx leaf cells in this code.
|
|
--library UNISIM;
|
|
--use UNISIM.VComponents.all;
|
|
|
|
entity counter_2bit is
|
|
Port ( CLK : in STD_LOGIC;
|
|
RST : in STD_LOGIC;
|
|
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
|
|
end counter_2bit;
|
|
|
|
architecture Behavioral of counter_2bit is
|
|
|
|
signal s_cnt : STD_LOGIC_VECTOR(1 downto 0) := "00";
|
|
begin
|
|
process(CLK, RST)
|
|
begin
|
|
if RST = '1' then
|
|
s_cnt <= "00";
|
|
elsif rising_edge(CLK) then
|
|
s_cnt <= s_cnt + 1;
|
|
end if;
|
|
end process;
|
|
COUNT_OUT <= s_cnt;
|
|
|
|
end Behavioral;
|