issue fixed, needs some redesign tho

.gitignore

@@ -29,3 +29,5 @@
 # Windows specific
 Thumbs.db
 Desktop.ini
+
+project_7/hx.exe

project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc

@@ -13,16 +13,17 @@ set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports {RST}]
 set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports {START}]
 
 set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports {SW_MODE}]
-#set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
-#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
+set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports {SW_STOP_SET}]
+set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports {SW_ALARM_SET}]
 #set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
 #set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
 #set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
-#set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
-#set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
-#set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
+#set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports {RST_B}]
+#set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports {RST_C}]
+# Stopky
+set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports {RST_C}]
 # Budik 
-set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports {SW_ALARM_SET}]
+set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports {RST_B}]
 set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[0]}]
 set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[1]}]
 set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[2]}]
@@ -30,7 +31,7 @@ set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[
 
 
 ## LEDs
-#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports {ALARM_LED}]
 #set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
 #set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
 #set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports {led[3]}]

project_7/project_5.srcs/sources_1/new/clock_logic.vhd

@@ -4,21 +4,13 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity clock_logic is
     Port ( 
         CLK        : in  STD_LOGIC;
         RST        : in  STD_LOGIC;
         CE_1HZ     : in  STD_LOGIC; -- Enable signal from the divider
-        SW_DIN     : in  STD_LOGIC_VECTOR (3 downto 0);
+        SW_DIN     : in  STD_LOGIC_VECTOR (3 downto 0); -- set data on btn_load
         BTN_LOAD   : in  STD_LOGIC_VECTOR (3 downto 0);
         -- Outputs to the top module/display
         S_UNITS    : out STD_LOGIC_VECTOR (3 downto 0);

project_7/project_5.srcs/sources_1/new/counter.vhd

@@ -1,37 +1,9 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 09.03.2026 15:14:35
--- Design Name: 
--- Module Name: counter - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
+-- project_7/project_5.srcs/sources_1/new/counter.vhd
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity counter is
     Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
     Port ( CLK : in STD_LOGIC;
@@ -71,4 +43,4 @@ begin
 
     COUNT_OUT <= s_cnt;
 
-end Behavioral;
+end Behavioral;

project_7/project_5.srcs/sources_1/new/display_drive.vhd

@@ -4,14 +4,6 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity display_driver is
     Port ( 

project_7/project_5.srcs/sources_1/new/top_modul.vhd

@@ -9,8 +9,11 @@ entity top_modul is
            START : in STD_LOGIC;
            SW_MODE  : in  STD_LOGIC; -- '0' = HH:MM, '1' = MM:SS
            SW_ALARM_SET  : in  STD_LOGIC; -- '0' = Display Clock, '1' = Set Alarm
+           SW_STOP_SET  : in  STD_LOGIC; -- '0' = Display Clock, '1' = Set Stopky
            SW_DIN   : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
            BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
+           RST_B : in STD_LOGIC;
+           RST_C : in STD_LOGIC;
            SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
            ANODS : out STD_LOGIC_VECTOR (3 downto 0);
            ALARM_LED : out STD_LOGIC -- LED lights up when alarm triggers
@@ -34,7 +37,7 @@ architecture Behavioral of top_modul is
     signal clk_400_Hz : std_logic;
     signal s_ce_units   : std_logic;
     
-    -- You MUST declare these signals so top_modul can carry data between the two submodules
+    -- Top_modul can carry data between the two submodules thanks to this
     signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0);
     signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0);
     signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0);
@@ -43,12 +46,27 @@ architecture Behavioral of top_modul is
     signal alrm_s_units, alrm_s_tens : std_logic_vector(3 downto 0);
     signal alrm_m_units, alrm_m_tens : std_logic_vector(3 downto 0);
     signal alrm_h_units, alrm_h_tens : std_logic_vector(3 downto 0);
+
+    -- stopky clock
+    signal stop_s_units, stop_s_tens : std_logic_vector(3 downto 0);
+    signal stop_m_units, stop_m_tens : std_logic_vector(3 downto 0);
+    signal stop_h_units, stop_h_tens : std_logic_vector(3 downto 0);
+    -- cap stopky clock
+    signal cap_s_units, cap_s_tens : std_logic_vector(3 downto 0);
+    signal cap_m_units, cap_m_tens : std_logic_vector(3 downto 0);
+    signal cap_h_units, cap_h_tens : std_logic_vector(3 downto 0);
     
     -- Signals to send to the display
     signal d0, d1, d2, d3 : std_logic_vector(3 downto 0);
 
     signal load_clock : std_logic_vector(3 downto 0);
     signal load_alarm : std_logic_vector(3 downto 0);
+    signal load_stopky : std_logic_vector(3 downto 0);
+
+    -- stopky ci behaju
+    signal stops_running : std_logic := '0';
+    signal stops_reset: std_logic := '0';
+    signal sw_stop_prev : std_logic := '0';
 begin
 
     U_DIV_1HZ : divider
@@ -100,20 +118,54 @@ begin
             H_TENS   => alrm_h_tens
         );
 
+    stops_running  <= s_ce_units;
+    stops_reset <= RST or RST_C;
+    -- Clock Engine submodule for stopky
+    U_STOPKY_CORE : entity work.clock_logic
+        port map (
+            CLK      => CLK,
+            RST      => stops_reset,
+            CE_1HZ   => stops_running,
+            SW_DIN   => "0000",
+            BTN_LOAD => "0000",
+            S_UNITS  => stop_s_units,
+            S_TENS   => stop_s_tens,
+            M_UNITS  => stop_m_units,
+            M_TENS   => stop_m_tens,
+            H_UNITS  => stop_h_units,
+            H_TENS   => stop_h_tens
+        );
+
     -- Comparator Logic for alarm LED to be ON or OFF
+    -- TODO BUG proste niekedy na zaciatku ledka svieti aj ked ma byt zhasnuta
     process(CLK)
     begin
         if rising_edge(CLK) then
+            sw_stop_prev <= SW_STOP_SET;
+            -- alarm
+            if RST = '1' or RST_B = '1' then
+                ALARM_LED <= '0';
             -- Match condition (HH:MM)
-            if (sig_h_tens = alrm_h_tens and sig_h_units = alrm_h_units and
+            elsif (START = '1' and 
+                sig_h_tens = alrm_h_tens and sig_h_units = alrm_h_units and
                 sig_m_tens = alrm_m_tens and sig_m_units = alrm_m_units and
                 sig_s_tens = "0000" and sig_s_units = "0000") then
                 ALARM_LED <= '1';
             end if;
-
-            -- Reset turns the alarm LED off
-            if RST = '1' then
-                ALARM_LED <= '0';
+            if RST = '1' or RST_C = '1' then
+                cap_s_units <= "0000";
+                cap_s_tens  <= "0000";
+                cap_m_units <= "0000";
+                cap_m_tens  <= "0000";
+                cap_h_units <= "0000";
+                cap_h_tens  <= "0000";
+            elsif SW_STOP_SET = '1' and sw_stop_prev = '0' then 
+                cap_s_units <= stop_s_units;
+                cap_s_tens  <= stop_s_tens;
+                cap_m_units <= stop_m_units;
+                cap_m_tens  <= stop_m_tens;
+                cap_h_units <= stop_h_units;
+                cap_h_tens  <= stop_h_tens;
             end if;
         end if;
     end process;
@@ -128,7 +180,8 @@ begin
     -- Mode Multiplexing (4 digit display)
     process(SW_ALARM_SET, SW_MODE, 
             sig_s_units, sig_s_tens, sig_m_units, sig_m_tens, sig_h_units, sig_h_tens,
-            alrm_m_units, alrm_m_tens, alrm_h_units, alrm_h_tens)
+            alrm_m_units, alrm_m_tens, alrm_h_units, alrm_h_tens, stop_s_units, stop_s_tens,
+            stop_m_units, stop_m_tens, stop_h_units, stop_h_tens )
     begin
         if SW_ALARM_SET = '1' then
             -- While setting alarm, always show Alarm HH:MM
@@ -136,6 +189,20 @@ begin
             d1 <= alrm_m_tens;
             d2 <= alrm_h_units;
             d3 <= alrm_h_tens;
+        elsif SW_STOP_SET = '1' then
+            if SW_MODE = '1' then
+                -- Stopky (MM:SS)
+                d0 <= cap_s_units;
+                d1 <= cap_s_tens;
+                d2 <= cap_m_units;
+                d3 <= cap_m_tens;
+            else
+                -- Stopky (HH:MM)
+                d0 <= cap_m_units;
+                d1 <= cap_m_tens;
+                d2 <= cap_h_units;
+                d3 <= cap_h_tens;
+            end if;
         else
             -- Normal Operation
             if SW_MODE = '1' then

project_7/project_5.xpr

@@ -177,6 +177,7 @@
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="top_modul"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">