stopky su hotove

project_7/project_5.srcs/sources_1/new/clock_logic.vhd

@@ -4,21 +4,13 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity clock_logic is
     Port ( 
         CLK        : in  STD_LOGIC;
         RST        : in  STD_LOGIC;
         CE_1HZ     : in  STD_LOGIC; -- Enable signal from the divider
-        SW_DIN     : in  STD_LOGIC_VECTOR (3 downto 0);
+        SW_DIN     : in  STD_LOGIC_VECTOR (3 downto 0); -- set data on btn_load
         BTN_LOAD   : in  STD_LOGIC_VECTOR (3 downto 0);
         -- Outputs to the top module/display
         S_UNITS    : out STD_LOGIC_VECTOR (3 downto 0);