hotovy priklad 5 funguje uplne bez problemov
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@@ -69,7 +69,21 @@ architecture Behavioral of top_modul is
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component decoder_an is
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Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
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ANODES : out STD_LOGIC_VECTOR (1 downto 0));
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ANODES : out STD_LOGIC_VECTOR (3 downto 0));
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end component;
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component mux is
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Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
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I1 : in STD_LOGIC_VECTOR (3 downto 0);
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I2 : in STD_LOGIC_VECTOR (3 downto 0);
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I3 : in STD_LOGIC_VECTOR (3 downto 0);
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S : in STD_LOGIC_VECTOR (1 downto 0);
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Y : out STD_LOGIC_VECTOR (3 downto 0));
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end component;
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component dec_seg is
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Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
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seg : out STD_LOGIC_VECTOR (7 downto 0));
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end component;
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signal clk_1_Hz : std_logic;
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@@ -80,6 +94,10 @@ architecture Behavioral of top_modul is
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signal s_cnt_tens : std_logic_vector(3 downto 0); -- To MUX I1
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signal s_cnt_2bit : std_logic_vector(1 downto 0);
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signal s_mux_out : std_logic_vector(3 downto 0);
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signal s_ce_units : std_logic;
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begin
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@@ -98,12 +116,13 @@ begin
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CLK_400_Hz => clk_400_Hz
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);
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s_ce_units <= clk_1_Hz and START;
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-- TOP COUNTER (Units)
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U_CNT_TOP : counter
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port map (
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CLK => CLK,
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RST => RST,
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CE => START,
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CE => s_ce_units,
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TC => s_tc_units,
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COUNT_OUT => s_cnt_units
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);
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@@ -130,6 +149,21 @@ begin
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SEL => s_cnt_2bit, -- 2-bitov<6F> sign<67>l
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ANODES => ANODS -- V<>stupn<70> port top modulu
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);
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U_MUX : mux
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port map (
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I0 => s_cnt_units, -- V<>stup z prv<72>ho <20><>ta<74>a
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I1 => s_cnt_tens, -- V<>stup z druh<75>ho <20><>ta<74>a
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I2 => "0000", -- Zatia<69> nevyu<79>it<69> (nula)
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I3 => "0000", -- Zatia<69> nevyu<79>it<69> (nula)
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S => s_cnt_2bit, -- Sign<67>l zo zelen<65>ho <20><>ta<74>a (v<>ber an<61>dy)
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Y => s_mux_out -- Vybran<61> <20><>slica pre segmenty
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);
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U_DEC_SEG : dec_seg
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port map (
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BCD => s_mux_out, -- <20><>slica vybran<61> multiplexerom
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SEG => SEGMENTS -- V<>stupn<70> port top modulu (8 bitov)
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);
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end Behavioral;
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