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hotovy priklad 5 funguje uplne bez problemov

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filipriec skolsky PC
2026-03-09 17:03:42 +01:00
parent db3b8977bf
commit a87a3896cc
6 changed files with 343 additions and 10 deletions
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58
project_5/project_5.srcs/sources_1/new/dec2.vhd Normal file
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@@ -0,0 +1,58 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:54:24
-- Design Name:
-- Module Name: dec_seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dec_seg is
Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);
SEG : out STD_LOGIC_VECTOR (7 downto 0));
end dec_seg;
architecture Behavioral of dec_seg is
begin
-- Konverzia BCD na 7-segment (ABCDEFG + DP)
-- Form<72>t: "ABCDEFG DP"
with bcd select
seg <= "11000000" when "0000", -- 0
"11111001" when "0001", -- 1
"10100100" when "0010", -- 2
"10110000" when "0011", -- 3
"10011001" when "0100", -- 4
"10010010" when "0101", -- 5
"10000010" when "0110", -- 6
"11111000" when "0111", -- 7
"10000000" when "1000", -- 8
"10010000" when "1001", -- 9
"11111111" when others; -- off
end Behavioral;

12
project_5/project_5.srcs/sources_1/new/decoder_bottom.vhd
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@@ -34,17 +34,17 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : in STD_LOGIC_VECTOR (3 downto 0));
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_an;
architecture Behavioral of decoder_an is
begin
with SEL select
ANODES <= "1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when "11",
"0000" when others;
ANODES <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when "11",
"1111" when others;
end Behavioral;

53
project_5/project_5.srcs/sources_1/new/mux.vhd Normal file
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@@ -0,0 +1,53 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:47:51
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end mux;
architecture Behavioral of mux is
begin
with S select
Y <= I0 when "00",
I1 when "01",
I2 when "10",
I3 when "11",
"0000" when others;
end Behavioral;

38
project_5/project_5.srcs/sources_1/new/top_modul.vhd
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@@ -69,7 +69,21 @@ architecture Behavioral of top_modul is
component decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : out STD_LOGIC_VECTOR (1 downto 0));
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component mux is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component dec_seg is
Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal clk_1_Hz : std_logic;
@@ -80,6 +94,10 @@ architecture Behavioral of top_modul is
signal s_cnt_tens : std_logic_vector(3 downto 0); -- To MUX I1
signal s_cnt_2bit : std_logic_vector(1 downto 0);
signal s_mux_out : std_logic_vector(3 downto 0);
signal s_ce_units : std_logic;
begin
@@ -98,12 +116,13 @@ begin
CLK_400_Hz => clk_400_Hz
);
s_ce_units <= clk_1_Hz and START;
-- TOP COUNTER (Units)
U_CNT_TOP : counter
port map (
CLK => CLK,
RST => RST,
CE => START,
CE => s_ce_units,
TC => s_tc_units,
COUNT_OUT => s_cnt_units
);
@@ -130,6 +149,21 @@ begin
SEL => s_cnt_2bit, -- 2-bitov<6F> sign<67>l
ANODES => ANODS -- V<>stupn<70> port top modulu
);
U_MUX : mux
port map (
I0 => s_cnt_units, -- V<>stup z prv<72>ho <20><>ta<74>a
I1 => s_cnt_tens, -- V<>stup z druh<75>ho <20><>ta<74>a
I2 => "0000", -- Zatia<69> nevyu<79>it<69> (nula)
I3 => "0000", -- Zatia<69> nevyu<79>it<69> (nula)
S => s_cnt_2bit, -- Sign<67>l zo zelen<65>ho <20><>ta<74>a (v<>ber an<61>dy)
Y => s_mux_out -- Vybran<61> <20><>slica pre segmenty
);
U_DEC_SEG : dec_seg
port map (
BCD => s_mux_out, -- <20><>slica vybran<61> multiplexerom
SEG => SEGMENTS -- V<>stupn<70> port top modulu (8 bitov)
);
end Behavioral;