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zmenene tlacitko na switch ked sa meni hodnota

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Priec
2026-05-08 16:30:05 +02:00
parent 5d2ce073c8
commit 99aea1652c
3 changed files with 33 additions and 48 deletions
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2
.gitignore vendored
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@@ -31,3 +31,5 @@ Thumbs.db
Desktop.ini
project_7/hx.exe
**/x.md

51
project_7/project_5.srcs/sources_1/new/clock_logic.vhd
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@@ -10,8 +10,8 @@ entity clock_logic is
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE_1HZ : in STD_LOGIC; -- Enable signal from the divider
SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- set data on btn_load
BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0);
DIGIT_SEL: in STD_LOGIC_VECTOR (3 downto 0); -- '0001'=M_UNITS, '0010'=M_TENS, atd.
BTN_INC : in STD_LOGIC; -- drzanie tlacidla pre inkrement
-- Outputs to the top module/display
S_UNITS : out STD_LOGIC_VECTOR (3 downto 0);
S_TENS : out STD_LOGIC_VECTOR (3 downto 0);
@@ -45,31 +45,16 @@ architecture Behavioral of clock_logic is
-- Reset for hours (to handle the 24 reset)
signal hour_reset : std_logic;
-- Specific load enable signals that check for boundaries
signal load_h_tens, load_h_units : std_logic;
signal load_m_tens, load_m_units : std_logic;
signal inc_m_units : std_logic;
signal inc_m_tens : std_logic;
signal inc_h_units : std_logic;
signal inc_h_tens : std_logic;
-- Internal signals for the "Safe" load triggers
signal safe_load_su, safe_load_st : std_logic;
signal safe_load_mu, safe_load_mt : std_logic;
signal safe_load_hu, safe_load_ht : std_logic;
begin
-- MINUTES CONSTRAINTS (Max 59)
load_m_units <= BTN_LOAD(0) when (SW_DIN <= "1001") else '0'; -- 0-9
load_m_tens <= BTN_LOAD(1) when (SW_DIN <= "0101") else '0'; -- 0-5
-- HOURS CONSTRAINTS (Max 23)
-- Rule A: Cannot load Tens > 2.
-- Rule B: If Tens is 2, cannot load Units > 3.
-- Rule C: If Units is > 3, cannot load Tens into 2.
load_h_tens <= BTN_LOAD(3) when (
SW_DIN < "0010" or
(SW_DIN = "0010" and sig_h_units <= "0011")
) else '0';
load_h_units <= BTN_LOAD(2) when (
(sig_h_tens < "0010" and SW_DIN <= "1001") or
(sig_h_tens = "0010" and SW_DIN <= "0011")
) else '0';
inc_m_units <= BTN_INC and DIGIT_SEL(0);
inc_m_tens <= BTN_INC and DIGIT_SEL(1);
inc_h_units <= BTN_INC and DIGIT_SEL(2);
inc_h_tens <= BTN_INC and DIGIT_SEL(3);
-------------------------------------------------------
-- SECONDS SECTION
@@ -109,8 +94,8 @@ begin
CLK => CLK,
RST => RST,
CE => tc_st,
PE => load_m_units,
DIN => SW_DIN,
PE => inc_m_units, -- for M_UNITS (bit 0)
DIN => "0001",
TC => tc_mu,
COUNT_OUT => sig_m_units
);
@@ -122,8 +107,8 @@ begin
CLK => CLK,
RST => RST,
CE => tc_mu,
PE => load_m_tens,
DIN => SW_DIN,
PE => inc_m_tens,
DIN => "0010",
TC => tc_mt,
COUNT_OUT => sig_m_tens
);
@@ -156,8 +141,8 @@ begin
CLK => CLK,
RST => hour_reset,
CE => tc_mt,
PE => load_h_units,
DIN => SW_DIN,
PE => inc_h_units,
DIN => "0100",
TC => tc_hu,
COUNT_OUT => sig_h_units
);
@@ -169,8 +154,8 @@ begin
CLK => CLK,
RST => hour_reset,
CE => tc_hu,
PE => load_h_tens,
DIN => SW_DIN,
PE => inc_h_tens,
DIN => "1000",
TC => open,
COUNT_OUT => sig_h_tens
);

24
project_7/project_5.srcs/sources_1/new/top_modul.vhd
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@@ -11,7 +11,8 @@ entity top_modul is
SW_ALARM_SET : in STD_LOGIC; -- '0' = Display Clock, '1' = Set Alarm
SW_STOP_SET : in STD_LOGIC; -- '0' = Display Clock, '1' = Set Stopky
SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
-- BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
SW_DIGIT_SEL : in STD_LOGIC_VECTOR (3 downto 0); -- '0001'=M_UNITS, '0010'=M_TENS, '0100'=H_UNITS, '1000'=H_TENS
RST_B : in STD_LOGIC;
RST_C : in STD_LOGIC;
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
@@ -59,9 +60,7 @@ architecture Behavioral of top_modul is
-- Signals to send to the display
signal d0, d1, d2, d3 : std_logic_vector(3 downto 0);
signal load_clock : std_logic_vector(3 downto 0);
signal load_alarm : std_logic_vector(3 downto 0);
signal load_stopky : std_logic_vector(3 downto 0);
signal btn_inc_pulse : std_logic;
-- stopky ci behaju
signal stops_running : std_logic := '0';
@@ -83,17 +82,16 @@ begin
CLK_400_Hz => clk_400_Hz
);
s_ce_units <= clk_1_Hz and START;
load_clock <= BTN_LOAD when SW_ALARM_SET = '0' else "0000";
load_alarm <= BTN_LOAD when SW_ALARM_SET = '1' else "0000";
s_ce_units <= clk_1_Hz and START and not SW_ALARM_SET;
btn_inc_pulse <= clk_1_Hz and SW_ALARM_SET;
-- Clock Engine submodule
U_CLOCK_CORE : entity work.clock_logic
port map (
CLK => CLK,
RST => RST,
CE_1HZ => s_ce_units,
SW_DIN => SW_DIN,
BTN_LOAD => load_clock,
DIGIT_SEL=> SW_DIN,
BTN_INC => btn_inc_pulse,
S_UNITS => sig_s_units,
S_TENS => sig_s_tens,
M_UNITS => sig_m_units,
@@ -108,8 +106,8 @@ begin
CLK => CLK,
RST => RST,
CE_1HZ => '0',
SW_DIN => SW_DIN,
BTN_LOAD => load_alarm,
DIGIT_SEL=> SW_DIN,
BTN_INC => btn_inc_pulse,
S_UNITS => alrm_s_units,
S_TENS => alrm_s_tens,
M_UNITS => alrm_m_units,
@@ -126,8 +124,8 @@ begin
CLK => CLK,
RST => stops_reset,
CE_1HZ => stops_running,
SW_DIN => "0000",
BTN_LOAD => "0000",
DIGIT_SEL => "0000",
BTN_INC => '0',
S_UNITS => stop_s_units,
S_TENS => stop_s_tens,
M_UNITS => stop_m_units,