filipriec/FPGA---VHDL
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

zmenene tlacitko na switch ked sa meni hodnota

Browse Source
This commit is contained in:
Priec
2026-05-08 16:30:05 +02:00
parent 5d2ce073c8
commit 99aea1652c
3 changed files with 33 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
project_7/project_5.srcs/sources_1/new/top_modul.vhd
View File

@@ -11,7 +11,8 @@ entity top_modul is
SW_ALARM_SET : in STD_LOGIC; -- '0' = Display Clock, '1' = Set Alarm
SW_STOP_SET : in STD_LOGIC; -- '0' = Display Clock, '1' = Set Stopky
SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
-- BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
SW_DIGIT_SEL : in STD_LOGIC_VECTOR (3 downto 0); -- '0001'=M_UNITS, '0010'=M_TENS, '0100'=H_UNITS, '1000'=H_TENS
RST_B : in STD_LOGIC;
RST_C : in STD_LOGIC;
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
@@ -59,9 +60,7 @@ architecture Behavioral of top_modul is
-- Signals to send to the display
signal d0, d1, d2, d3 : std_logic_vector(3 downto 0);
signal load_clock : std_logic_vector(3 downto 0);
signal load_alarm : std_logic_vector(3 downto 0);
signal load_stopky : std_logic_vector(3 downto 0);
signal btn_inc_pulse : std_logic;
-- stopky ci behaju
signal stops_running : std_logic := '0';
@@ -83,17 +82,16 @@ begin
CLK_400_Hz => clk_400_Hz
);
s_ce_units <= clk_1_Hz and START;
load_clock <= BTN_LOAD when SW_ALARM_SET = '0' else "0000";
load_alarm <= BTN_LOAD when SW_ALARM_SET = '1' else "0000";
s_ce_units <= clk_1_Hz and START and not SW_ALARM_SET;
btn_inc_pulse <= clk_1_Hz and SW_ALARM_SET;
-- Clock Engine submodule
U_CLOCK_CORE : entity work.clock_logic
port map (
CLK => CLK,
RST => RST,
CE_1HZ => s_ce_units,
SW_DIN => SW_DIN,
BTN_LOAD => load_clock,
DIGIT_SEL=> SW_DIN,
BTN_INC => btn_inc_pulse,
S_UNITS => sig_s_units,
S_TENS => sig_s_tens,
M_UNITS => sig_m_units,
@@ -108,8 +106,8 @@ begin
CLK => CLK,
RST => RST,
CE_1HZ => '0',
SW_DIN => SW_DIN,
BTN_LOAD => load_alarm,
DIGIT_SEL=> SW_DIN,
BTN_INC => btn_inc_pulse,
S_UNITS => alrm_s_units,
S_TENS => alrm_s_tens,
M_UNITS => alrm_m_units,
@@ -126,8 +124,8 @@ begin
CLK => CLK,
RST => stops_reset,
CE_1HZ => stops_running,
SW_DIN => "0000",
BTN_LOAD => "0000",
DIGIT_SEL => "0000",
BTN_INC => '0',
S_UNITS => stop_s_units,
S_TENS => stop_s_tens,
M_UNITS => stop_m_units,