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project_6/project_6.srcs/sources_1/new/decoder_bottom.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.03.2026 15:39:11
+-- Design Name: 
+-- Module Name: decoder_bottom - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity decoder_an is
+    Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
+           ANODES : out STD_LOGIC_VECTOR (3 downto 0));
+end decoder_an;
+
+architecture Behavioral of decoder_an is
+
+begin
+    with SEL select
+        ANODES <= "1110" when "00",
+                  "1101" when "01",
+                  "1011" when "10",
+                  "0111" when "11",
+                  "1111" when others;
+
+end Behavioral;