working z predoslych hodin

project_3_nzio/project_3_nzio.srcs/sources_1/new/COUNTER.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 02.03.2026 13:52:15
+-- Design Name: 
+-- Module Name: divider - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+
+entity counter is
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           CE : in std_logic;
+           COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
+end counter;
+
+architecture Behavioral of counter is
+
+signal div_cnt : STD_LOGIC_VECTOR (3 downto 0);
+
+begin
+
+DIV: process (CLK, CE, RST, div_cnt)
+begin
+    if (RST = '1') then
+        div_cnt <= (others => '0');
+    elsif ((CLK = '1') and (CLK'event)) then
+        if (CE = '1') then
+            if (div_cnt < "1111") then
+                div_cnt <= div_cnt +1;
+            else
+                div_cnt <= (others => '0');
+            end if;
+        end if;
+    end if;
+end process;
+
+COUNT_OUT <= div_cnt;
+   
+end Behavioral;

project_3_nzio/project_3_nzio.srcs/sources_1/new/divider.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 02.03.2026 13:52:15
+-- Design Name: 
+-- Module Name: divider - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity divider is
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           CLK_1_Hz : out STD_LOGIC);
+end divider;
+
+architecture Behavioral of divider is
+
+signal div_cnt : STD_LOGIC_VECTOR (26 downto 0);
+signal ce : STD_LOGIC;
+
+begin
+
+DIV: process (CLK, RST, div_cnt)
+begin
+    if (RST = '1') then
+        div_cnt <= (others => '0');
+    elsif ((CLK = '1') and (CLK'event)) then
+            if (div_cnt < "0101111101011110000011111111") then
+                div_cnt <= div_cnt +1;
+            else
+                div_cnt <= (others => '0');
+            end if;
+    end if;
+end process;
+
+
+BUFGCE_inst_0 : BUFGCE
+   port map (
+      O => CLK_1_Hz,   -- 1-bit output: Clock output
+      CE => ce, -- 1-bit input: Clock enable input for I0
+      I => CLK    -- 1-bit input: Primary clock
+   );
+
+ce <= '1' when div_cnt = "0101111101011110000011111111" 
+            else '0';
+   
+end Behavioral;

project_3_nzio/project_3_nzio.srcs/sources_1/new/top_modul.vhd

@@ -0,0 +1,77 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 02.03.2026 14:36:06
+-- Design Name: 
+-- Module Name: top_modul - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top_modul is
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           CE : in STD_LOGIC;
+           LEDS : out STD_LOGIC_VECTOR (3 downto 0));
+end top_modul;
+
+
+
+architecture Behavioral of top_modul is
+
+
+component divider is
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           CLK_1_Hz : out STD_LOGIC);
+end component;
+
+component counter is
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           CE : in std_logic;
+           COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
+end component;
+
+signal clk_1_hz : std_logic;
+begin
+
+divider_inst_0 : divider
+   port map (
+      CLK => CLK,   -- 1-bit output: Clock output
+      RST => RST, -- 1-bit input: Clock enable input for I0
+      CLK_1_Hz => clk_1_hz    -- 1-bit input: Primary clock
+   );
+
+counter_inst_0 : counter
+    port map ( CLK => clk_1_hz,
+                RST => RST,
+                CE => CE,
+                COUNT_OUT => LEDS
+                );
+                
+
+end Behavioral;