working z predoslych hodin

project_2/project_2.srcs/sim_1/new/modul_x.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 02.03.2026 12:53:10
+-- Design Name: 
+-- Module Name: top_modul_test - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+entity top_modul_test is
+    Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);
+           ANODS : out STD_LOGIC_VECTOR (3 downto 0);
+           SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0));
+end top_modul_test;
+
+architecture Behavioral of top_modul_test is
+
+component top_modul_test is
+    Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);
+           ANODS : out STD_LOGIC_VECTOR (3 downto 0);
+           SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0));
+end component;
+
+constant TIME_DELTA : time := 10ns;
+
+signal SW_tb : STD_LOGIC_VECTOR (3 downto 0);
+signal ANODS_tb : STD_LOGIC_VECTOR (3 downto 0);
+signal SEGMENTS_tb : STD_LOGIC_VECTOR (7 downto 0);
+
+begin
+
+top_modul_inst_0: top_modul_test 
+    port map ( SW => SW_tb,
+                ANODS => ANODS_tb,
+                SEGMENTS => SEGMENTS_tb
+                );
+
+simulation: process 
+begin
+    SW_tb <= "0000";
+    ANODS_tb <= "0001";
+    wait for TIME_DELTA;
+    SW_tb <= "0000";
+    wait for TIME_DELTA;
+    SW_tb <= "0001";
+    wait for TIME_DELTA;
+    SW_tb <= "0010";
+    wait for TIME_DELTA;
+    SW_tb <= "0011";
+    wait for TIME_DELTA;
+    SW_tb <= "0111";
+    wait for TIME_DELTA;
+    SW_tb <= "0101";
+    wait for TIME_DELTA;
+    SW_tb <= "1111";
+    wait;
+end process;
+
+end Behavioral;

project_2/project_2.srcs/sim_1/new/top_model_test.vhd

@@ -0,0 +1,84 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 02.03.2026 12:53:10
+-- Design Name: 
+-- Module Name: top_modul_test - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+entity top_modul_test is
+    Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);
+           ANODS : out STD_LOGIC_VECTOR (3 downto 0);
+           SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0));
+end top_modul_test;
+
+architecture Behavioral of top_modul_test is
+
+component top_modul_test is
+    Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);
+           ANODS : out STD_LOGIC_VECTOR (3 downto 0);
+           SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0));
+end component;
+
+constant TIME_DELTA : time := 10ns;
+
+signal SW_tb : STD_LOGIC_VECTOR (3 downto 0);
+signal ANODS_tb : STD_LOGIC_VECTOR (3 downto 0);
+signal SEGMENTS_tb : STD_LOGIC_VECTOR (7 downto 0);
+
+begin
+
+top_modul_inst_0: top_modul_test 
+    port map ( SW => SW_tb,
+                ANODS => ANODS_tb,
+                SEGMENTS => SEGMENTS_tb
+                );
+
+simulation: process 
+begin
+    SW_tb <= "0000";
+    ANODS_tb <= "0001";
+    wait for TIME_DELTA;
+    SW_tb <= "0000";
+    wait for TIME_DELTA;
+    SW_tb <= "0001";
+    wait for TIME_DELTA;
+    SW_tb <= "0010";
+    wait for TIME_DELTA;
+    SW_tb <= "0011";
+    wait for TIME_DELTA;
+    SW_tb <= "0111";
+    wait for TIME_DELTA;
+    SW_tb <= "0101";
+    wait for TIME_DELTA;
+    SW_tb <= "1111";
+    wait;
+end process;
+
+end Behavioral;