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semestralka hotovo

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filipriec skolsky PC
2026-05-11 14:54:16 +02:00
parent 99aea1652c
commit 532382e4fa
5 changed files with 168 additions and 26 deletions
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18
project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc
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@@ -24,10 +24,10 @@ set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {SW_ALAR
set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {RST_C}]
# Budik
set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {RST_B}]
set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[0]}]
set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[1]}]
set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[2]}]
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[3]}]
set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {SW_DIGIT_SEL[0]}]
set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIGIT_SEL[1]}]
set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIGIT_SEL[2]}]
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {SW_DIGIT_SEL[3]}]
## LEDs
@@ -66,15 +66,15 @@ set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[2]
set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[3]}]
##Buttons
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports BTN_INC]
# btnU -> Hours Tens
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[3]}]
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[3]}]
# btnL -> Hours Units
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[2]}]
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[2]}]
# btnR -> Minutes Tens
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[1]}]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[1]}]
# btnD -> Minutes Units
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[0]}]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[0]}]
##Pmod Header JA

110
project_7/project_5.srcs/sources_1/new/alarm_led.vhd Normal file
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@@ -0,0 +1,110 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11.05.2026 13:34:01
-- Design Name:
-- Module Name: alarm_led - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alarm_led is
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE_1HZ : in STD_LOGIC;
ALARM_ACTIVE : in STD_LOGIC;
LED_OUT : out STD_LOGIC
);
end alarm_led;
architecture Behavioral of alarm_led is
component counter is
Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" );
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
PE : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR(3 downto 0);
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
signal blink_count : std_logic_vector(3 downto 0);
signal blink_rst : std_logic;
signal tc_9s : std_logic;
signal is_finished : std_logic := '0';
signal cycles : std_logic_vector(3 downto 0);
begin
blink_rst <= RST or (not ALARM_ACTIVE);
U_TIMER_9S : counter
generic map ( MAX_LIMIT => "1000" )
port map (
CLK => CLK,
RST => blink_rst,
CE => CE_1HZ,
PE => '0',
DIN => "0000",
TC => tc_9s,
COUNT_OUT => blink_count
);
U_CYCLE_COUNTER : counter
generic map ( MAX_LIMIT => "0010" ) -- 0, 1, 2
port map (
CLK => CLK,
RST => blink_rst,
CE => tc_9s,
PE => '0',
DIN => "0000",
TC => open,
COUNT_OUT => cycles
);
process(CLK)
begin
if rising_edge(CLK) then
if blink_rst = '1' then
is_finished <= '0';
elsif tc_9s = '1' and cycles = "0010" then
is_finished <= '1';
end if;
end if;
end process;
LED_OUT <= '1' when (ALARM_ACTIVE = '1' and is_finished = '0' and blink_count <= "0101")
else '0';
end Behavioral;

18
project_7/project_5.srcs/sources_1/new/clock_logic.vhd
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@@ -3,7 +3,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clock_logic is
Port (
@@ -50,12 +50,20 @@ architecture Behavioral of clock_logic is
signal inc_h_units : std_logic;
signal inc_h_tens : std_logic;
signal next_mu, next_mt, next_hu, next_ht : std_logic_vector(3 downto 0);
begin
inc_m_units <= BTN_INC and DIGIT_SEL(0);
inc_m_tens <= BTN_INC and DIGIT_SEL(1);
inc_h_units <= BTN_INC and DIGIT_SEL(2);
inc_h_tens <= BTN_INC and DIGIT_SEL(3);
-- MAX_LIMIT respektovanie pocas BTN_INC
next_mu <= "0000" when sig_m_units = "1001" else std_logic_vector(unsigned(sig_m_units) + 1);
next_mt <= "0000" when sig_m_tens = "0101" else std_logic_vector(unsigned(sig_m_tens) + 1);
next_hu <= "0000" when sig_h_units = "1001" else std_logic_vector(unsigned(sig_h_units) + 1);
next_ht <= "0000" when sig_h_tens = "0010" else std_logic_vector(unsigned(sig_h_tens) + 1);
-------------------------------------------------------
-- SECONDS SECTION
-- SECONDS UNITS (0-9) - Triggered by the 1Hz pulse
@@ -95,7 +103,7 @@ begin
RST => RST,
CE => tc_st,
PE => inc_m_units, -- for M_UNITS (bit 0)
DIN => "0001",
DIN => next_mu,
TC => tc_mu,
COUNT_OUT => sig_m_units
);
@@ -108,7 +116,7 @@ begin
RST => RST,
CE => tc_mu,
PE => inc_m_tens,
DIN => "0010",
DIN => next_mt,
TC => tc_mt,
COUNT_OUT => sig_m_tens
);
@@ -142,7 +150,7 @@ begin
RST => hour_reset,
CE => tc_mt,
PE => inc_h_units,
DIN => "0100",
DIN => next_hu,
TC => tc_hu,
COUNT_OUT => sig_h_units
);
@@ -155,7 +163,7 @@ begin
RST => hour_reset,
CE => tc_hu,
PE => inc_h_tens,
DIN => "1000",
DIN => next_ht,
TC => open,
COUNT_OUT => sig_h_tens
);

38
project_7/project_5.srcs/sources_1/new/top_modul.vhd
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@@ -10,7 +10,8 @@ entity top_modul is
SW_MODE : in STD_LOGIC; -- '0' = HH:MM, '1' = MM:SS
SW_ALARM_SET : in STD_LOGIC; -- '0' = Display Clock, '1' = Set Alarm
SW_STOP_SET : in STD_LOGIC; -- '0' = Display Clock, '1' = Set Stopky
SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
BTN_INC : in STD_LOGIC;
-- SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
-- BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
SW_DIGIT_SEL : in STD_LOGIC_VECTOR (3 downto 0); -- '0001'=M_UNITS, '0010'=M_TENS, '0100'=H_UNITS, '1000'=H_TENS
RST_B : in STD_LOGIC;
@@ -59,6 +60,8 @@ architecture Behavioral of top_modul is
-- Signals to send to the display
signal d0, d1, d2, d3 : std_logic_vector(3 downto 0);
signal pulse_to_clock : std_logic;
signal pulse_to_alarm : std_logic;
signal btn_inc_pulse : std_logic;
@@ -66,8 +69,14 @@ architecture Behavioral of top_modul is
signal stops_running : std_logic := '0';
signal stops_reset: std_logic := '0';
signal sw_stop_prev : std_logic := '0';
-- led
signal sig_alarm_active : std_logic := '0';
begin
pulse_to_clock <= clk_1_Hz and BTN_INC and (not SW_ALARM_SET) and (not SW_STOP_SET);
pulse_to_alarm <= clk_1_Hz and BTN_INC and SW_ALARM_SET;
U_DIV_1HZ : divider
port map (
CLK => CLK,
@@ -83,15 +92,15 @@ begin
);
s_ce_units <= clk_1_Hz and START and not SW_ALARM_SET;
btn_inc_pulse <= clk_1_Hz and SW_ALARM_SET;
btn_inc_pulse <= clk_1_Hz and SW_ALARM_SET and BTN_INC;
-- Clock Engine submodule
U_CLOCK_CORE : entity work.clock_logic
port map (
CLK => CLK,
RST => RST,
CE_1HZ => s_ce_units,
DIGIT_SEL=> SW_DIN,
BTN_INC => btn_inc_pulse,
DIGIT_SEL=> SW_DIGIT_SEL,
BTN_INC => pulse_to_clock,
S_UNITS => sig_s_units,
S_TENS => sig_s_tens,
M_UNITS => sig_m_units,
@@ -106,8 +115,8 @@ begin
CLK => CLK,
RST => RST,
CE_1HZ => '0',
DIGIT_SEL=> SW_DIN,
BTN_INC => btn_inc_pulse,
DIGIT_SEL=> SW_DIGIT_SEL,
BTN_INC => pulse_to_alarm,
S_UNITS => alrm_s_units,
S_TENS => alrm_s_tens,
M_UNITS => alrm_m_units,
@@ -142,13 +151,13 @@ begin
sw_stop_prev <= SW_STOP_SET;
-- alarm
if RST = '1' or RST_B = '1' then
ALARM_LED <= '0';
sig_alarm_active <= '0';
-- Match condition (HH:MM)
elsif (START = '1' and
elsif (START = '1' and SW_ALARM_SET = '0' and
sig_h_tens = alrm_h_tens and sig_h_units = alrm_h_units and
sig_m_tens = alrm_m_tens and sig_m_units = alrm_m_units and
sig_s_tens = "0000" and sig_s_units = "0000") then
ALARM_LED <= '1';
sig_s_tens = "0000" and sig_s_units = "0001") then
sig_alarm_active <= '1';
end if;
if RST = '1' or RST_C = '1' then
cap_s_units <= "0000";
@@ -168,6 +177,15 @@ begin
end if;
end process;
U_ALARM_BLINKER : entity work.alarm_led
port map (
CLK => CLK,
RST => RST,
CE_1HZ => clk_1_Hz,
ALARM_ACTIVE => sig_alarm_active,
LED_OUT => ALARM_LED
);
-- -- Mode Multiplexing
-- -- If SW_MODE = '1', show MM:SS. If '0', show HH:MM.
-- d0 <= sig_s_units when SW_MODE = '1' else sig_m_units;

6
project_7/project_5.xpr
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@@ -92,6 +92,12 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/alarm_led.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/clock_logic.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>