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project_7/project_5.srcs/sources_1/new/top_modul.vhd

@@ -10,7 +10,8 @@ entity top_modul is
            SW_MODE  : in  STD_LOGIC; -- '0' = HH:MM, '1' = MM:SS
            SW_ALARM_SET  : in  STD_LOGIC; -- '0' = Display Clock, '1' = Set Alarm
            SW_STOP_SET  : in  STD_LOGIC; -- '0' = Display Clock, '1' = Set Stopky
-           SW_DIN   : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
+           BTN_INC : in STD_LOGIC;
+           -- SW_DIN   : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
            -- BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
            SW_DIGIT_SEL : in STD_LOGIC_VECTOR (3 downto 0); -- '0001'=M_UNITS, '0010'=M_TENS, '0100'=H_UNITS, '1000'=H_TENS
            RST_B : in STD_LOGIC;
@@ -59,6 +60,8 @@ architecture Behavioral of top_modul is
     
     -- Signals to send to the display
     signal d0, d1, d2, d3 : std_logic_vector(3 downto 0);
+    signal pulse_to_clock : std_logic;
+    signal pulse_to_alarm : std_logic;
 
     signal btn_inc_pulse : std_logic;
 
@@ -66,8 +69,14 @@ architecture Behavioral of top_modul is
     signal stops_running : std_logic := '0';
     signal stops_reset: std_logic := '0';
     signal sw_stop_prev : std_logic := '0';
+    
+    -- led
+    signal sig_alarm_active : std_logic := '0';
 begin
 
+    pulse_to_clock <= clk_1_Hz and BTN_INC and (not SW_ALARM_SET) and (not SW_STOP_SET);
+    pulse_to_alarm <= clk_1_Hz and BTN_INC and SW_ALARM_SET;
+    
     U_DIV_1HZ : divider
         port map (
             CLK => CLK,
@@ -83,15 +92,15 @@ begin
         );
 
     s_ce_units <= clk_1_Hz and START and not SW_ALARM_SET;
-    btn_inc_pulse <= clk_1_Hz and SW_ALARM_SET;
+    btn_inc_pulse <= clk_1_Hz and SW_ALARM_SET and BTN_INC;
     -- Clock Engine submodule
     U_CLOCK_CORE : entity work.clock_logic
         port map (
             CLK      => CLK,
             RST      => RST,
             CE_1HZ   => s_ce_units,
-            DIGIT_SEL=> SW_DIN,
-            BTN_INC  => btn_inc_pulse,
+            DIGIT_SEL=> SW_DIGIT_SEL,
+            BTN_INC  => pulse_to_clock,
             S_UNITS  => sig_s_units,
             S_TENS   => sig_s_tens,
             M_UNITS  => sig_m_units,
@@ -106,8 +115,8 @@ begin
             CLK      => CLK,
             RST      => RST,
             CE_1HZ   => '0',
-            DIGIT_SEL=> SW_DIN,
-            BTN_INC  => btn_inc_pulse,
+            DIGIT_SEL=> SW_DIGIT_SEL,
+            BTN_INC  => pulse_to_alarm,
             S_UNITS  => alrm_s_units,
             S_TENS   => alrm_s_tens,
             M_UNITS  => alrm_m_units,
@@ -142,13 +151,13 @@ begin
             sw_stop_prev <= SW_STOP_SET;
             -- alarm
             if RST = '1' or RST_B = '1' then
-                ALARM_LED <= '0';
+                sig_alarm_active <= '0';
             -- Match condition (HH:MM)
-            elsif (START = '1' and 
+            elsif (START = '1' and SW_ALARM_SET = '0' and 
                 sig_h_tens = alrm_h_tens and sig_h_units = alrm_h_units and
                 sig_m_tens = alrm_m_tens and sig_m_units = alrm_m_units and
-                sig_s_tens = "0000" and sig_s_units = "0000") then
-                ALARM_LED <= '1';
+                sig_s_tens = "0000" and sig_s_units = "0001") then
+                sig_alarm_active <= '1';
             end if;
             if RST = '1' or RST_C = '1' then
                 cap_s_units <= "0000";
@@ -167,6 +176,15 @@ begin
             end if;
         end if;
     end process;
+    
+    U_ALARM_BLINKER : entity work.alarm_led
+        port map (
+            CLK          => CLK,
+            RST          => RST,
+            CE_1HZ       => clk_1_Hz,
+            ALARM_ACTIVE => sig_alarm_active,
+            LED_OUT      => ALARM_LED 
+        );
 
     -- -- Mode Multiplexing
     -- -- If SW_MODE = '1', show MM:SS. If '0', show HH:MM.