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project_7/project_5.srcs/sources_1/new/alarm_led.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 11.05.2026 13:34:01
+-- Design Name: 
+-- Module Name: alarm_led - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity alarm_led is
+    Port ( 
+        CLK           : in  STD_LOGIC;
+        RST           : in  STD_LOGIC; 
+        CE_1HZ        : in  STD_LOGIC; 
+        ALARM_ACTIVE  : in  STD_LOGIC;
+        LED_OUT       : out STD_LOGIC
+    );
+end alarm_led;
+
+architecture Behavioral of alarm_led is
+
+    component counter is
+        Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" );
+        Port ( 
+            CLK       : in  STD_LOGIC;
+            RST       : in  STD_LOGIC;
+            CE        : in  STD_LOGIC;
+            PE        : in  STD_LOGIC;
+            DIN       : in  STD_LOGIC_VECTOR(3 downto 0);
+            TC        : out STD_LOGIC;
+            COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)
+        );
+    end component;
+
+    signal blink_count : std_logic_vector(3 downto 0);
+    signal blink_rst   : std_logic;
+    signal tc_9s       : std_logic; 
+    signal is_finished : std_logic := '0';
+    signal cycles      : std_logic_vector(3 downto 0);
+
+    
+begin
+
+    blink_rst <= RST or (not ALARM_ACTIVE);
+
+    U_TIMER_9S : counter
+        generic map ( MAX_LIMIT => "1000" ) 
+        port map (
+            CLK       => CLK,
+            RST       => blink_rst,
+            CE        => CE_1HZ,
+            PE        => '0',
+            DIN       => "0000",
+            TC        => tc_9s,
+            COUNT_OUT => blink_count
+        );
+
+    U_CYCLE_COUNTER : counter
+        generic map ( MAX_LIMIT => "0010" ) -- 0, 1, 2
+        port map (
+            CLK       => CLK,
+            RST       => blink_rst,
+            CE        => tc_9s,
+            PE        => '0',
+            DIN       => "0000",
+            TC        => open,
+            COUNT_OUT => cycles
+        );
+
+    process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if blink_rst = '1' then
+                is_finished <= '0';
+            elsif tc_9s = '1' and cycles = "0010" then
+                is_finished <= '1';
+            end if;
+        end if;
+    end process;
+
+
+    LED_OUT <= '1' when (ALARM_ACTIVE = '1' and is_finished = '0' and blink_count <= "0101") 
+               else '0';
+end Behavioral;