working buttons and DIN to control display

project_7/project_5.srcs/sources_1/new/top_modul.vhd

@@ -35,6 +35,8 @@ entity top_modul is
     Port ( CLK : in STD_LOGIC;
            RST : in STD_LOGIC;
            START : in STD_LOGIC;
+           SW_DIN   : in STD_LOGIC_VECTOR (3 downto 0); -- The value to set
+           BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
            SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
            ANODS : out STD_LOGIC_VECTOR (3 downto 0));
 end top_modul;
@@ -57,6 +59,8 @@ architecture Behavioral of top_modul is
 	    Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
         Port ( CLK : in STD_LOGIC;
                CE : in STD_LOGIC;
+               PE : in STD_LOGIC;
+               DIN : in STD_LOGIC_VECTOR(3 downto 0);
                RST : in STD_LOGIC;
                TC : out STD_LOGIC;
                COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
@@ -129,6 +133,8 @@ begin
             CLK       => CLK,
             RST       => RST,
             CE        => s_ce_units,
+            PE => BTN_LOAD(0),
+            DIN => SW_DIN,
             TC        => tc_mu,
             COUNT_OUT => sig_m_units
         );
@@ -140,6 +146,8 @@ begin
             CLK       => CLK,
             RST       => RST,
             CE        => tc_mu,
+            PE => BTN_LOAD(1),
+            DIN => SW_DIN,
             TC        => tc_mt,
             COUNT_OUT => sig_m_tens
         );
@@ -154,6 +162,8 @@ begin
             CLK       => CLK,
             RST       => hour_reset,
             CE        => tc_mt,
+            PE => BTN_LOAD(2),
+            DIN => SW_DIN,
             TC        => tc_hu,
             COUNT_OUT => sig_h_units
         );
@@ -165,6 +175,8 @@ begin
             CLK       => CLK,
             RST       => hour_reset,
             CE        => tc_hu,
+            PE => BTN_LOAD(3),
+            DIN => SW_DIN,
             TC        => open,
             COUNT_OUT => sig_h_tens
         );