workinghod 6 a hod7

project_7/project_5.srcs/sources_1/new/top_modul.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.03.2026 14:40:14
+-- Design Name: 
+-- Module Name: top_modul - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top_modul is
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           START : in STD_LOGIC;
+           SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
+           ANODS : out STD_LOGIC_VECTOR (3 downto 0));
+end top_modul;
+
+architecture Behavioral of top_modul is
+    
+    component divider is
+        Port ( CLK : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
+    end component;
+    
+    component divider_400Hz is
+        Port ( CLK : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
+    end component;
+    
+	component counter is
+	    Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
+        Port ( CLK : in STD_LOGIC;
+               CE : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               TC : out STD_LOGIC;
+               COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
+    end component;
+    
+    component counter_2bit is
+        Port ( CLK : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
+    end component;
+
+    component decoder_an is
+        Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
+               ANODES : out STD_LOGIC_VECTOR (3 downto 0));
+    end component;
+
+    component mux is
+        Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
+               I1 : in STD_LOGIC_VECTOR (3 downto 0);
+               I2 : in STD_LOGIC_VECTOR (3 downto 0);
+               I3 : in STD_LOGIC_VECTOR (3 downto 0);
+               S  : in STD_LOGIC_VECTOR (1 downto 0);
+               Y  : out STD_LOGIC_VECTOR (3 downto 0));
+    end component;
+    
+    component dec_seg is
+        Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
+               seg : out STD_LOGIC_VECTOR (7 downto 0));
+    end component;
+
+    signal clk_1_Hz   : std_logic;
+    signal clk_400_Hz : std_logic;
+
+    signal s_ce_units   : std_logic;
+	-- Internal signals to connect the counters
+    signal sig_m_units : std_logic_vector(3 downto 0);
+    signal sig_m_tens  : std_logic_vector(3 downto 0);
+    signal sig_h_units : std_logic_vector(3 downto 0);
+    signal sig_h_tens  : std_logic_vector(3 downto 0);
+    -- Carry signals (TC)
+    signal tc_mu, tc_mt, tc_hu : std_logic;
+    -- Reset for hours (to handle the 24 reset)
+    signal hour_reset : std_logic;
+    
+    signal s_cnt_2bit   : std_logic_vector(1 downto 0);
+    signal s_mux_out : std_logic_vector(3 downto 0);
+
+begin
+
+    U_DIV : divider
+        port map (
+            CLK => CLK,
+            RST => RST,
+            CLK_1_Hz => clk_1_Hz
+        );
+        
+        
+    U_DIV_400Hz : divider_400Hz
+        port map (
+            CLK => CLK,
+            RST => RST,
+            CLK_400_Hz => clk_400_Hz
+        );
+        
+    s_ce_units <= clk_1_Hz and START;
+	-- MINUTES UNITS (0-9)
+    U_CNT_MIN_UNITS : counter
+        generic map ( MAX_LIMIT => "1001" ) -- To 9
+        port map (
+            CLK       => CLK,
+            RST       => RST,
+            CE        => s_ce_units,
+            TC        => tc_mu,
+            COUNT_OUT => sig_m_units
+        );
+
+    -- MINUTES TENS (0-5)
+    U_CNT_MIN_TENS : counter
+        generic map ( MAX_LIMIT => "0101" ) -- To 5
+        port map (
+            CLK       => CLK,
+            RST       => RST,
+            CE        => tc_mu,
+            TC        => tc_mt,
+            COUNT_OUT => sig_m_tens
+        );
+
+    -- Logic to reset hours at 24:00
+    hour_reset <= '1' when (RST = '1' or (sig_h_tens = "0010" and sig_h_units = "0011" and tc_mt = '1')) else '0';
+    
+    -- HOURS UNITS (0-9)
+    U_CNT_HOR_UNITS : counter
+        generic map ( MAX_LIMIT => "1001" ) -- To 9
+        port map (
+            CLK       => CLK,
+            RST       => hour_reset,
+            CE        => tc_mt,
+            TC        => tc_hu,
+            COUNT_OUT => sig_h_units
+        );
+
+    -- HOURS TENS (0-2)
+    U_CNT_HOR_TENS : counter
+        generic map ( MAX_LIMIT => "0010" ) -- To 2
+        port map (
+            CLK       => CLK,
+            RST       => hour_reset,
+            CE        => tc_hu,
+            TC        => open,
+            COUNT_OUT => sig_h_tens
+        );
+
+    U_CNT_2BIT : counter_2bit
+        port map (
+            CLK       => clk_400_Hz,
+            RST       => RST,
+            COUNT_OUT => s_cnt_2bit
+        );      
+        
+    U_DEC_ANODES : decoder_an
+        port map (
+            SEL    => s_cnt_2bit,
+            ANODES => ANODS  
+        );
+
+    U_MUX : mux
+        port map (
+	        I0 => sig_m_units,
+            I1 => sig_m_tens,
+            I2 => sig_h_units,
+            I3 => sig_h_tens,
+            S  => s_cnt_2bit, 
+            Y  => s_mux_out 
+        );
+        
+    U_DEC_SEG : dec_seg
+        port map (
+            BCD => s_mux_out,
+            SEG => SEGMENTS 
+        );        
+                
+end Behavioral;