workinghod 6 a hod7

project_7/project_5.srcs/sources_1/new/counter_ones.vhd

@@ -0,0 +1,37 @@
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity cnt_0_9 is
+    Port ( CLK : in STD_LOGIC;
+           CE : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           TC : out STD_LOGIC;
+           COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
+end cnt_0_9;
+
+architecture Behavioral of cnt_0_9 is
+    -- Internal signal to keep track of the current number
+    signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
+begin
+
+    process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if RST = '1' then
+                s_cnt <= "0000";
+            elsif CE = '1' then
+                if s_cnt = "1001" then -- If we are at 9
+                    s_cnt <= "0000";   -- Reset to 0
+                else
+                    s_cnt <= s_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    COUNT_OUT <= s_cnt;
+
+end Behavioral;