filipriec

filipriec pushed to master at filipriec/projekt1

2025-12-01 14:08:07 +00:00

d47060e5dd final renamed to mqtt

filipriec pushed to master at filipriec/stm32_rust

2025-11-29 18:30:28 +00:00

f7063f877d working buffered hardware uart from previous project is now on

9c7f67b071 template for semestralka2

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filipriec pushed to master at filipriec/stm32_rust

2025-11-28 18:20:08 +00:00

6f27f98a38 final uml

a61b808176 finalized plantuml

4ff73644c6 uml

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filipriec pushed to master at filipriec/stm32_rust

2025-11-25 06:57:00 +00:00

f6d83a0acc updated lock file

3e2ad6eb7d timing uml diagrams added

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filipriec pushed to master at filipriec/stm32_rust

2025-11-23 23:22:02 +00:00

6d694c840b cleanup

filipriec pushed to master at filipriec/stm32_rust

2025-11-23 22:12:35 +00:00

522236e20c removed redundant code

804dc66a4b sampling only in the middle

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filipriec pushed to master at filipriec/stm32_rust

2025-11-23 20:58:10 +00:00

9451bc5ae9 timer HAL

e5e4d13ff6 prod1

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filipriec pushed to master at filipriec/stm32_rust

2025-11-23 15:25:30 +00:00

d0ddea119d Add global target ignore

348c4e63d9 library now fully functional and working

3218714d8c software uart lib errors fixed

4097ce1c7a software uart is now a library

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filipriec pushed to master at filipriec/pvs

2025-11-20 20:42:03 +00:00

ca7eac70e4 movement class

3e47f855ed cleaning

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filipriec pushed to master at filipriec/stm32_rust

2025-11-20 12:28:17 +00:00

685067a75f jsut minor changes, UNTESTED DMA TIMER CHANGE

filipriec pushed tag v1.9.0 to filipriec/stm32_rust

2025-11-19 23:03:42 +00:00

filipriec pushed to master at filipriec/stm32_rust

2025-11-19 23:03:42 +00:00

179bec6ed6 finished and fully functional

8e1c2ec29f time to do final merge

e569fbc39d dma used to transfer Tx

24d1da44aa working at the baud rate 600

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filipriec pushed to master at filipriec/stm32_rust

2025-11-19 19:40:34 +00:00

ef56483016 improved parsing of software uart

de4e04787b max frequency fixed it all

78c85c7982 tweaked parameters, storing before increasing frequencies

bf34ff1bcb faster and smarter DMA

e2378cd436 working with DMA at 9600

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filipriec pushed to master at filipriec/stm32_rust

2025-11-19 11:51:53 +00:00

da2f011682 1d needs to be builded again from scratch

b339b34e4d toggling bit and reading it now works properly well

9c26a0ca81 not working interrupt via tim7 to read data

c5bee53a30 toggle in the interrupt is working

7a8a308620 now im reading proper buffer

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filipriec pushed to master at filipriec/stm32_rust

2025-11-18 21:56:45 +00:00

516309aed2 proper printing of the pipe_int tx_pipe

filipriec pushed to master at filipriec/stm32_rust

2025-11-18 18:43:16 +00:00

45df1e87e4 testing, not owrking 1d yet

0a0ff0f38a debugging more

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filipriec pushed to master at filipriec/stm32_rust

2025-11-18 12:36:43 +00:00

1909497403 hopefuly working CPU transfer to bsrr

filipriec pushed to master at filipriec/stm32_rust

2025-11-18 09:29:34 +00:00

c01a908b25 cpu polling instead of dma

filipriec pushed to master at filipriec/stm32_rust

2025-11-18 09:12:11 +00:00

c0bc36bec2 rx bez dma ready for testing

filipriec pushed to master at filipriec/stm32_rust

2025-11-18 08:21:53 +00:00

66c4741afa blbosti

fa343624e7 tx stale nefunguje

66521896b3 moving things around, time to debug crap out of it

a0c30894ee better registers for Rx

16c66ee1ff final debug

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