757 lines
22 KiB
Rust
757 lines
22 KiB
Rust
// stm32u5xx-hal/src/rcc.rs
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//! Reset and Clock Control for STM32U575 (initial/minimal port)
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//!
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//! Scope: only features that clearly overlap between stm32l4xx-hal rcc.rs
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//! and the STM32U5 HAL C (stm32u5xx_hal_rcc.c/.h).
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//!
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//! Skipped (present in U5 HAL C, not here yet):
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//! - MSIK (kernel MSI), SHSI (secure HSI)
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//! - PLL2 / PLL3
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//! - PLL FRACN and MBOOST/EPOD handling
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//! - LSE glitch filter, LSE CSS, LSESYS
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//! - LSI divider (LSIPREDIV)
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//! - STOP wake-up clock selection (STOPWUCK / STOPKERWUCK)
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//! - Security/privileged attributes
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//! - APB3 (PCLK3) prescaler & clocks
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//! - MCO configuration
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//! - Per-peripheral Enable/Reset tables (normally in rcc/enable.rs)
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use crate::pac::{rcc, RCC};
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use crate::flash::ACR;
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use crate::pwr::Pwr;
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use crate::time::Hertz;
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use fugit::RateExtU32;
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// Uncomment when you add bus-peripheral enable/reset mapping like in L4
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// mod enable;
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum MsiFreq {
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// Order and names reflect STM32U5 MSIRANGE mapping (RCC_MSIRANGE_x):
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// 0..15 encode the specific frequencies per stm32u5xx_hal_rcc.h
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// We provide exact frequencies in Hz.
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MSI48, // 48_000_000
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MSI24, // 24_000_000
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MSI16, // 16_000_000
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MSI12, // 12_000_000
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MSI4, // 4_000_000
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MSI2, // 2_000_000
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MSI1_33, // 1_330_000 (approx 1.33 MHz)
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MSI1, // 1_000_000
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MSI3_072, // 3_072_000
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MSI1_536, // 1_536_000
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MSI1_024, // 1_024_000
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MSI_768K, // 768_000
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MSI400K, // 400_000
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MSI200K, // 200_000
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MSI133K, // 133_000
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MSI100K, // 100_000
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}
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impl MsiFreq {
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fn to_hertz(self) -> Hertz {
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let hz = match self {
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Self::MSI48 => 48_000_000,
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Self::MSI24 => 24_000_000,
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Self::MSI16 => 16_000_000,
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Self::MSI12 => 12_000_000,
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Self::MSI4 => 4_000_000,
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Self::MSI2 => 2_000_000,
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Self::MSI1_33 => 1_330_000,
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Self::MSI1 => 1_000_000,
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Self::MSI3_072 => 3_072_000,
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Self::MSI1_536 => 1_536_000,
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Self::MSI1_024 => 1_024_000,
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Self::MSI_768K => 768_000,
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Self::MSI400K => 400_000,
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Self::MSI200K => 200_000,
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Self::MSI133K => 133_000,
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Self::MSI100K => 100_000,
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};
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hz.Hz()
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}
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// Map to ICSCR1.MSISRANGE field encoding (0..15)
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fn to_range_bits(self) -> u8 {
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match self {
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Self::MSI48 => 0,
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Self::MSI24 => 1,
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Self::MSI16 => 2,
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Self::MSI12 => 3,
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Self::MSI4 => 4,
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Self::MSI2 => 5,
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Self::MSI1_33 => 6,
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Self::MSI1 => 7,
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Self::MSI3_072 => 8,
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Self::MSI1_536 => 9,
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Self::MSI1_024 => 10,
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Self::MSI_768K => 11,
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Self::MSI400K => 12,
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Self::MSI200K => 13,
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Self::MSI133K => 14,
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Self::MSI100K => 15,
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}
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}
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}
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/// Extension trait that constrains the `RCC` peripheral
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pub trait RccExt {
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/// Constrains the `RCC` peripheral so it plays nicely with the other abstractions
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fn constrain(self) -> Rcc;
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}
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impl RccExt for RCC {
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fn constrain(self) -> Rcc {
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Rcc {
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ahb1: AHB1::new(),
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ahb2_1: AHB2_1::new(),
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ahb2_2: AHB2_2::new(),
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ahb3: AHB3::new(),
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apb1r1: APB1R1::new(),
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apb1r2: APB1R2::new(),
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apb2: APB2::new(),
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apb3: APB3::new(),
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cfgr: CFGR {
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hse: None,
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lse: None,
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msi: None,
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hsi48: false,
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lsi: false,
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hclk: None,
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pclk1: None,
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pclk2: None,
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sysclk: None,
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pll_source: None,
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pll_config: None,
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},
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}
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}
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}
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/// Constrained RCC peripheral
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pub struct Rcc {
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pub ahb1: AHB1,
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pub ahb2_1: AHB2_1,
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pub ahb2_2: AHB2_2,
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pub ahb3: AHB3,
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pub apb1r1: APB1R1,
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pub apb1r2: APB1R2,
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pub apb2: APB2,
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pub apb3: APB3,
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pub cfgr: CFGR,
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}
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/// Backup domain control register proxy
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pub struct BDCR {
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_0: (),
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}
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impl BDCR {
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#[allow(dead_code)]
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pub(crate) fn bdcr(&mut self) -> &rcc::BDCR {
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unsafe { &(*RCC::ptr()).bdcr }
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}
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}
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/// Control/Status Register proxy
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pub struct CSR {
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_0: (),
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}
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impl CSR {
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#[allow(dead_code)]
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pub(crate) fn csr(&mut self) -> &rcc::CSR {
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unsafe { &(*RCC::ptr()).csr }
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}
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}
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macro_rules! bus_struct_1 {
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($busX:ident => ($EN:ident, $en:ident, $SMEN:ident, $smen:ident, $RST:ident, $rst:ident, $doc:literal),) => {
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#[doc = $doc]
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pub struct $busX {
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_0: (),
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}
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impl $busX {
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pub(crate) fn new() -> Self {
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Self { _0: () }
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}
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#[allow(unused)]
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pub(crate) fn enr(&self) -> &rcc::$EN {
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unsafe { &(*RCC::ptr()).$en }
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}
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#[allow(unused)]
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pub(crate) fn smenr(&self) -> &rcc::$SMEN {
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unsafe { &(*RCC::ptr()).$smen }
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}
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#[allow(unused)]
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pub(crate) fn rstr(&self) -> &rcc::$RST {
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unsafe { &(*RCC::ptr()).$rst }
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}
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}
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};
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}
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// U5 splits AHB2/APB1 into *1/*2 register banks; we model both.
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bus_struct_1! {
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AHB1 => (AHB1ENR, ahb1enr, AHB1SMENR, ahb1smenr, AHB1RSTR, ahb1rstr, "AHB1 registers"),
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}
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bus_struct_1! {
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AHB2_1 => (AHB2ENR1, ahb2enr1, AHB2SMENR1, ahb2smenr1, AHB2RSTR1, ahb2rstr1, "AHB2 part 1 registers"),
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}
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bus_struct_1! {
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AHB2_2 => (AHB2ENR2, ahb2enr2, AHB2SMENR2, ahb2smenr2, AHB2RSTR2, ahb2rstr2, "AHB2 part 2 registers"),
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}
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bus_struct_1! {
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AHB3 => (AHB3ENR, ahb3enr, AHB3SMENR, ahb3smenr, AHB3RSTR, ahb3rstr, "AHB3 registers"),
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}
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bus_struct_1! {
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APB1R1 => (APB1ENR1, apb1enr1, APB1SMENR1, apb1smenr1, APB1RSTR1, apb1rstr1, "APB1 register set 1"),
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}
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bus_struct_1! {
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APB1R2 => (APB1ENR2, apb1enr2, APB1SMENR2, apb1smenr2, APB1RSTR2, apb1rstr2, "APB1 register set 2"),
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}
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bus_struct_1! {
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APB2 => (APB2ENR, apb2enr, APB2SMENR, apb2smenr, APB2RSTR, apb2rstr, "APB2 registers"),
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}
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bus_struct_1! {
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APB3 => (APB3ENR, apb3enr, APB3SMENR, apb3smenr, APB3RSTR, apb3rstr, "APB3 registers"),
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}
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/// Bus associated to peripheral
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pub trait RccBus: crate::Sealed {
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type Bus;
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}
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/// Enable/disable peripheral
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pub trait Enable: RccBus {
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fn enable(bus: &mut Self::Bus);
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fn disable(bus: &mut Self::Bus);
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fn is_enabled() -> bool;
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fn is_disabled() -> bool;
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unsafe fn enable_unchecked();
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unsafe fn disable_unchecked();
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}
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/// Enable/disable peripheral in sleep mode
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pub trait SMEnable: RccBus {
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fn enable_in_sleep_mode(bus: &mut Self::Bus);
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fn disable_in_sleep_mode(bus: &mut Self::Bus);
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fn is_enabled_in_sleep_mode() -> bool;
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fn is_disabled_in_sleep_mode() -> bool;
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unsafe fn enable_in_sleep_mode_unchecked();
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unsafe fn disable_in_sleep_mode_unchecked();
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}
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/// Reset peripheral
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pub trait Reset: RccBus {
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fn reset(bus: &mut Self::Bus);
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unsafe fn reset_unchecked();
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}
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#[derive(Debug, PartialEq)]
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struct HseConfig {
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speed: u32,
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bypass: CrystalBypass,
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css: ClockSecuritySystem,
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}
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#[derive(Debug, PartialEq)]
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struct LseConfig {
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bypass: CrystalBypass,
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// Skipped: LSE CSS / glitch filter / LSESYS
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css: ClockSecuritySystem, // kept in struct for future, not applied
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}
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/// Crystal bypass selector
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CrystalBypass {
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Enable,
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Disable,
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}
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/// Clock Security System
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ClockSecuritySystem {
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Enable,
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Disable,
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}
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const HSI: u32 = 16_000_000; // Hz (HSI16)
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/// PLL Source (PLL1)
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PllSource {
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MSI,
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HSI16,
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HSE,
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}
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impl PllSource {
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// Map to RCC_PLL1CFGR PLL1SRC field bits (00: none, 01: MSI, 10: HSI, 11: HSE)
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fn to_pllsrc_bits(self) -> u8 {
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match self {
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Self::MSI => 0b01,
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Self::HSI16 => 0b10,
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Self::HSE => 0b11,
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}
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}
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}
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#[derive(Clone, Copy, Debug)]
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pub struct PllConfig {
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// Main PLL division factor M (1..16) -> register stores (M-1)
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m: u8,
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// Main PLL multiplication factor N (4..512) -> register stores (N-1)
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n: u16,
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// Main PLL division factor for PLLR (system clock) (1..128) -> reg stores (R-1)
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r: u8,
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// Skipped: P, Q outputs, MBOOST, FRACN, RGE beyond minimal
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}
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impl PllConfig {
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pub fn new(m: u8, n: u16, r: u8) -> Self {
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assert!(m >= 1 && m <= 16);
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assert!(n >= 4 && n <= 512);
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assert!(r >= 1 && r <= 128);
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Self { m, n, r }
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}
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}
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/// Clock configuration builder
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pub struct CFGR {
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hse: Option<HseConfig>,
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lse: Option<LseConfig>,
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msi: Option<MsiFreq>,
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hsi48: bool,
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lsi: bool,
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hclk: Option<u32>,
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pclk1: Option<u32>,
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pclk2: Option<u32>,
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sysclk: Option<u32>,
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pll_source: Option<PllSource>,
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pll_config: Option<PllConfig>,
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}
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impl CFGR {
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pub fn hse(mut self, freq: Hertz, bypass: CrystalBypass, css: ClockSecuritySystem) -> Self {
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self.hse = Some(HseConfig {
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speed: freq.raw(),
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bypass,
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css,
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});
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self
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}
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pub fn lse(mut self, bypass: CrystalBypass, css: ClockSecuritySystem) -> Self {
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self.lse = Some(LseConfig { bypass, css });
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self
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}
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pub fn msi(mut self, range: MsiFreq) -> Self {
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self.msi = Some(range);
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self
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}
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pub fn lsi(mut self, on: bool) -> Self {
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self.lsi = on;
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self
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}
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pub fn hsi48(mut self, on: bool) -> Self {
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self.hsi48 = on;
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self
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}
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pub fn hclk(mut self, freq: Hertz) -> Self {
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self.hclk = Some(freq.raw());
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self
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}
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pub fn pclk1(mut self, freq: Hertz) -> Self {
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self.pclk1 = Some(freq.raw());
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self
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}
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pub fn pclk2(mut self, freq: Hertz) -> Self {
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self.pclk2 = Some(freq.raw());
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self
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}
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pub fn sysclk(mut self, freq: Hertz) -> Self {
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self.sysclk = Some(freq.raw());
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self
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}
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pub fn sysclk_with_pll(mut self, freq: Hertz, cfg: PllConfig) -> Self {
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self.sysclk = Some(freq.raw());
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self.pll_config = Some(cfg);
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self
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}
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pub fn pll_source(mut self, source: PllSource) -> Self {
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self.pll_source = Some(source);
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self
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}
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pub fn freeze(&self, acr: &mut ACR, pwr: &mut Pwr) -> Clocks {
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let rcc = unsafe { &*RCC::ptr() };
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// Ensure MSI is ON and selected first (safe base)
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if rcc.cr.read().msison().bit_is_clear() {
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rcc.cr.modify(|_, w| w.msison().set_bit());
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while rcc.cr.read().msisrdy().bit_is_clear() {}
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}
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// Program MSI to 4 MHz as default base (MSIRGSEL=1, MSISRANGE=4MHz)
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unsafe {
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rcc.icscr1.modify(|_, w| {
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w.msirgsel().set_bit();
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w.msisrange().bits(MsiFreq::MSI4.to_range_bits());
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w
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});
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}
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// If SYSCLK not MSI, force switch to MSI (SW=00) and wait
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if rcc.cfgr1.read().sws().bits() != 0 {
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// Reset CFGR1.SW to MSI
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rcc.cfgr1.modify(|_, w| unsafe { w.sw().bits(0b00) });
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while rcc.cfgr1.read().sws().bits() != 0b00 {}
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}
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//
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// 1) Oscillators
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//
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// LSI if requested (or if we needed by LSE CSS in future)
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let lsi_used = if self.lsi {
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rcc.bdcr.modify(|_, w| w.lsion().set_bit());
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while rcc.bdcr.read().lsirdy().bit_is_clear() {}
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true
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} else {
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false
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};
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// LSE if requested
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if let Some(lse_cfg) = &self.lse {
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// Enable backup domain write access
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// NOTE: depends on your Pwr wrapper; mirrors L4 HAL style
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pwr.cr1.reg().modify(|_, w| w.dbp().set_bit());
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// Enable LSE (bypass if set)
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if lse_cfg.bypass == CrystalBypass::Enable {
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rcc.bdcr.modify(|_, w| w.lsebyp().set_bit());
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}
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rcc.bdcr.modify(|_, w| w.lseon().set_bit());
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while rcc.bdcr.read().lserdy().bit_is_clear() {}
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// Skipped: LSESYS and LSE CSS/glitch filter
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}
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// HSE if requested
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if let Some(hse_cfg) = &self.hse {
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rcc.cr.modify(|_, w| {
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if hse_cfg.bypass == CrystalBypass::Enable {
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w.hsebyp().set_bit();
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}
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w.hseon().set_bit()
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});
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while rcc.cr.read().hserdy().bit_is_clear() {}
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if hse_cfg.css == ClockSecuritySystem::Enable {
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// Enable CSS on HSE (CR.CSSON)
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rcc.cr.modify(|_, w| w.csson().set_bit());
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}
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}
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// MSI range if set explicitly
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if let Some(msi) = self.msi {
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unsafe {
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rcc.icscr1.modify(|_, w| {
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w.msirgsel().set_bit();
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w.msisrange().bits(msi.to_range_bits());
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w
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})
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};
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while rcc.cr.read().msisrdy().bit_is_clear() {}
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}
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// HSI48
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if self.hsi48 {
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rcc.cr.modify(|_, w| w.hsi48on().set_bit());
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while rcc.cr.read().hsi48rdy().bit_is_clear() {}
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}
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//
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// 2) PLL1 setup (optional)
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//
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// Decide PLL1 source
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let (src_freq, pll_src) = if let Some(src) = self.pll_source {
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match src {
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PllSource::HSE => {
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let hse = self
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.hse
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.as_ref()
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.expect("HSE selected as PLL source, but not enabled");
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(hse.speed, src)
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}
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PllSource::HSI16 => (HSI, src),
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PllSource::MSI => {
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let msi = self.msi.expect("MSI selected as PLL source, but not enabled");
|
|
(msi.to_hertz().raw(), src)
|
|
}
|
|
}
|
|
} else {
|
|
if let Some(hse) = &self.hse {
|
|
(hse.speed, PllSource::HSE)
|
|
} else if let Some(msi) = self.msi {
|
|
(msi.to_hertz().raw(), PllSource::MSI)
|
|
} else {
|
|
(HSI, PllSource::HSI16)
|
|
}
|
|
};
|
|
|
|
// If we need HSI for PLL1 and it's not on, turn it on
|
|
if pll_src == PllSource::HSI16 {
|
|
rcc.cr.modify(|_, w| w.hsion().set_bit());
|
|
while rcc.cr.read().hsirdy().bit_is_clear() {}
|
|
}
|
|
|
|
let want_sysclk = match (self.sysclk, self.msi) {
|
|
(Some(sysclk), _) => sysclk,
|
|
(None, Some(msi)) => msi.to_hertz().raw(),
|
|
(None, None) => MsiFreq::MSI4.to_hertz().raw(),
|
|
};
|
|
|
|
assert!(want_sysclk <= 80_000_000);
|
|
|
|
// Auto PLL config if not provided (simple best-effort: M=1, R=2)
|
|
let pllconf = if self.pll_config.is_none() {
|
|
if self.sysclk.is_some() {
|
|
let m = 1u8;
|
|
let r = 2u8;
|
|
// want_sysclk = (src/m)*N / r => N = want_sysclk * r / (src/m)
|
|
let n = ((want_sysclk as u64) * (r as u64) / (src_freq as u64)) as u16;
|
|
Some(PllConfig::new(m, n, r))
|
|
} else {
|
|
None
|
|
}
|
|
} else {
|
|
self.pll_config
|
|
};
|
|
|
|
// Compute prescalers from requested hclk/pclk1/pclk2
|
|
// HPRE (CFGR2.HPRE), PPRE1/PPRE2 (CFGR2.PPRE1/PPRE2)
|
|
let (hpre_bits, hpre_div) = self
|
|
.hclk
|
|
.map(|hclk| match want_sysclk / hclk {
|
|
0 => unreachable!(),
|
|
1 => (0b0000, 1),
|
|
2 => (0b1000, 2),
|
|
3..=5 => (0b1001, 4),
|
|
6..=11 => (0b1010, 8),
|
|
12..=39 => (0b1011, 16),
|
|
40..=95 => (0b1100, 64),
|
|
96..=191 => (0b1101, 128),
|
|
192..=383 => (0b1110, 256),
|
|
_ => (0b1111, 512),
|
|
})
|
|
.unwrap_or((0b0000, 1));
|
|
let hclk = want_sysclk / hpre_div;
|
|
|
|
let (ppre1_bits, ppre1_div) = self
|
|
.pclk1
|
|
.map(|pclk1| match hclk / pclk1 {
|
|
0 => unreachable!(),
|
|
1 => (0b000, 1),
|
|
2 => (0b100, 2),
|
|
3..=5 => (0b101, 4),
|
|
6..=11 => (0b110, 8),
|
|
_ => (0b111, 16),
|
|
})
|
|
.unwrap_or((0b000, 1));
|
|
let pclk1 = hclk / (ppre1_div as u32);
|
|
|
|
let (ppre2_bits, ppre2_div) = self
|
|
.pclk2
|
|
.map(|pclk2| match hclk / pclk2 {
|
|
0 => unreachable!(),
|
|
1 => (0b000, 1),
|
|
2 => (0b100, 2),
|
|
3..=5 => (0b101, 4),
|
|
6..=11 => (0b110, 8),
|
|
_ => (0b111, 16),
|
|
})
|
|
.unwrap_or((0b000, 1));
|
|
let pclk2 = hclk / (ppre2_div as u32);
|
|
|
|
// Timer clocks double if APB prescaler != 1
|
|
let timclk1 = if ppre1_div == 1 { pclk1 } else { 2 * pclk1 };
|
|
let timclk2 = if ppre2_div == 1 { pclk2 } else { 2 * pclk2 };
|
|
|
|
// Adjust Flash latency (simple L4-like thresholds for <=80 MHz)
|
|
unsafe {
|
|
acr.acr().write(|w| {
|
|
w.latency().bits(if hclk <= 16_000_000 {
|
|
0b000
|
|
} else if hclk <= 32_000_000 {
|
|
0b001
|
|
} else if hclk <= 48_000_000 {
|
|
0b010
|
|
} else if hclk <= 64_000_000 {
|
|
0b011
|
|
} else {
|
|
0b100
|
|
})
|
|
})
|
|
}
|
|
|
|
// Program prescalers first (CFGR2: HPRE/PPRE1/PPRE2)
|
|
rcc.cfgr2.modify(|_, w| unsafe {
|
|
w.hpre().bits(hpre_bits);
|
|
w.ppre1().bits(ppre1_bits);
|
|
w.ppre2().bits(ppre2_bits)
|
|
});
|
|
|
|
let mut used_msi = self.msi;
|
|
let sysclk_src_bits;
|
|
|
|
if let Some(pll) = pllconf {
|
|
// Basic checks for VCO ranges (very simplified; FRACN/MBOOST ignored)
|
|
let vco_in = (src_freq as u32) / (pll.m as u32);
|
|
assert!(vco_in >= 1_000_000 && vco_in <= 16_000_000);
|
|
let vco = (vco_in as u64) * (pll.n as u64);
|
|
assert!(vco >= 128_000_000 && vco <= 544_000_000);
|
|
let sysclk_calc = (vco / (pll.r as u64)) as u32;
|
|
assert!(sysclk_calc <= 80_000_000);
|
|
|
|
// Disable PLL1 before reconfig
|
|
rcc.cr.modify(|_, w| w.pll1on().clear_bit());
|
|
while rcc.cr.read().pll1rdy().bit_is_set() {}
|
|
|
|
// Set PLL source
|
|
let src_bits = pll_src.to_pllsrc_bits();
|
|
rcc.pll1cfgr.modify(|_, w| unsafe {
|
|
w.pll1src().bits(src_bits);
|
|
// VCI range selection (very rough): 4..8 => range0, 8..16 => range1
|
|
let rge = if vco_in < 8_000_000 { 0b00 } else { 0b11 };
|
|
w.pll1rge().bits(rge);
|
|
// M
|
|
w.pll1m().bits(pll.m - 1);
|
|
// Enable only R output
|
|
w.pll1ren().clear_bit(); // clear first; will set after lock
|
|
w
|
|
});
|
|
|
|
// Program N, R in PLL1DIVR
|
|
rcc.pll1divr.modify(|_, w| unsafe {
|
|
w.pll1n().bits((pll.n - 1) as u16);
|
|
w.pll1r().bits(pll.r - 1);
|
|
// Leave P/Q untouched/disabled (skipped)
|
|
w
|
|
});
|
|
|
|
// Enable PLL1
|
|
rcc.cr.modify(|_, w| w.pll1on().set_bit());
|
|
while rcc.cr.read().pll1rdy().bit_is_clear() {}
|
|
|
|
// Enable PLL1 R output
|
|
rcc.pll1cfgr.modify(|_, w| w.pll1ren().set_bit());
|
|
|
|
// Switch SYSCLK to PLL1 (CFGR1.SW = 11)
|
|
sysclk_src_bits = 0b11;
|
|
rcc.cfgr1.modify(|_, w| unsafe { w.sw().bits(sysclk_src_bits) });
|
|
} else {
|
|
// Keep MSI as SYSCLK (CFGR1.SW = 00)
|
|
sysclk_src_bits = 0b00;
|
|
if used_msi.is_none() {
|
|
used_msi = Some(MsiFreq::MSI4);
|
|
}
|
|
rcc.cfgr1.modify(|_, w| unsafe { w.sw().bits(sysclk_src_bits) });
|
|
}
|
|
|
|
// Wait for SWS
|
|
while rcc.cfgr1.read().sws().bits() != sysclk_src_bits {}
|
|
|
|
// If we ended up on PLL, and MSI wasn't requested for other purposes, we can switch MSI off
|
|
if used_msi.is_none() && sysclk_src_bits == 0b11 {
|
|
rcc.cr.modify(|_, w| w.msison().clear_bit());
|
|
}
|
|
|
|
Clocks {
|
|
hclk: hclk.Hz(),
|
|
lsi: lsi_used,
|
|
lse: self.lse.is_some(),
|
|
msi: used_msi,
|
|
hsi48: self.hsi48,
|
|
pclk1: pclk1.Hz(),
|
|
pclk2: pclk2.Hz(),
|
|
ppre1: ppre1_div as u8,
|
|
ppre2: ppre2_div as u8,
|
|
sysclk: want_sysclk.Hz(),
|
|
timclk1: timclk1.Hz(),
|
|
timclk2: timclk2.Hz(),
|
|
pll_source: if pllconf.is_some() { Some(pll_src) } else { None },
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Frozen clock frequencies (indicate RCC config is locked)
|
|
#[derive(Clone, Copy, Debug)]
|
|
pub struct Clocks {
|
|
hclk: Hertz,
|
|
hsi48: bool,
|
|
msi: Option<MsiFreq>,
|
|
lsi: bool,
|
|
lse: bool,
|
|
pclk1: Hertz,
|
|
pclk2: Hertz,
|
|
ppre1: u8,
|
|
ppre2: u8,
|
|
sysclk: Hertz,
|
|
timclk1: Hertz,
|
|
timclk2: Hertz,
|
|
pll_source: Option<PllSource>,
|
|
}
|
|
|
|
impl Clocks {
|
|
pub fn hclk(&self) -> Hertz {
|
|
self.hclk
|
|
}
|
|
pub fn hsi48(&self) -> bool {
|
|
self.hsi48
|
|
}
|
|
pub fn msi(&self) -> Option<MsiFreq> {
|
|
self.msi
|
|
}
|
|
pub fn lsi(&self) -> bool {
|
|
self.lsi
|
|
}
|
|
pub fn lse(&self) -> bool {
|
|
self.lse
|
|
}
|
|
pub fn pclk1(&self) -> Hertz {
|
|
self.pclk1
|
|
}
|
|
pub fn pclk2(&self) -> Hertz {
|
|
self.pclk2
|
|
}
|
|
pub fn pll_source(&self) -> Option<PllSource> {
|
|
self.pll_source
|
|
}
|
|
#[allow(dead_code)]
|
|
pub(crate) fn ppre1(&self) -> u8 {
|
|
self.ppre1
|
|
}
|
|
#[allow(dead_code)]
|
|
pub(crate) fn ppre2(&self) -> u8 {
|
|
self.ppre2
|
|
}
|
|
pub fn sysclk(&self) -> Hertz {
|
|
self.sysclk
|
|
}
|
|
pub fn timclk1(&self) -> Hertz {
|
|
self.timclk1
|
|
}
|
|
pub fn timclk2(&self) -> Hertz {
|
|
self.timclk2
|
|
}
|
|
}
|