From ae298c150e13fb96eddfd461cfc12195ba05f342 Mon Sep 17 00:00:00 2001 From: Priec Date: Sun, 19 Oct 2025 13:31:52 +0200 Subject: [PATCH] last 2 errors --- src/rcc/rcc.rs | 76 +++++++++++++++++++++++++------------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/src/rcc/rcc.rs b/src/rcc/rcc.rs index 7d4cec6..07897e0 100644 --- a/src/rcc/rcc.rs +++ b/src/rcc/rcc.rs @@ -149,7 +149,7 @@ pub struct BDCR { impl BDCR { #[allow(dead_code)] pub(crate) fn bdcr(&mut self) -> &rcc::BDCR { - unsafe { &(*RCC::ptr()).bdcr } + unsafe { &(*RCC::ptr()).bdcr() } } } @@ -161,7 +161,7 @@ pub struct CSR { impl CSR { #[allow(dead_code)] pub(crate) fn csr(&mut self) -> &rcc::CSR { - unsafe { &(*RCC::ptr()).csr } + unsafe { &(*RCC::ptr()).csr() } } } @@ -177,15 +177,15 @@ macro_rules! bus_struct_1 { } #[allow(unused)] pub(crate) fn enr(&self) -> &rcc::$EN { - unsafe { &(*RCC::ptr()).$en } + unsafe { &(*RCC::ptr()).$en() } } #[allow(unused)] pub(crate) fn smenr(&self) -> &rcc::$SMEN { - unsafe { &(*RCC::ptr()).$smen } + unsafe { &(*RCC::ptr()).$smen() } } #[allow(unused)] pub(crate) fn rstr(&self) -> &rcc::$RST { - unsafe { &(*RCC::ptr()).$rst } + unsafe { &(*RCC::ptr()).$rst() } } } }; @@ -397,14 +397,14 @@ impl CFGR { let rcc = unsafe { &*RCC::ptr() }; // Ensure MSI is ON and selected first (safe base) - if rcc.cr.read().msison().bit_is_clear() { - rcc.cr.modify(|_, w| w.msison().set_bit()); - while rcc.cr.read().msisrdy().bit_is_clear() {} + if rcc.cr().read().msison().bit_is_clear() { + rcc.cr().modify(|_, w| w.msison().set_bit()); + while rcc.cr().read().msisrdy().bit_is_clear() {} } // Program MSI to 4 MHz as default base (MSIRGSEL=1, MSISRANGE=4MHz) unsafe { - rcc.icscr1.modify(|_, w| { + rcc.icscr1().modify(|_, w| { w.msirgsel().set_bit(); w.msisrange().bits(MsiFreq::MSI4.to_range_bits()); w @@ -412,10 +412,10 @@ impl CFGR { } // If SYSCLK not MSI, force switch to MSI (SW=00) and wait - if rcc.cfgr1.read().sws().bits() != 0 { + if rcc.cfgr1().read().sws().bits() != 0 { // Reset CFGR1.SW to MSI - rcc.cfgr1.modify(|_, w| unsafe { w.sw().bits(0b00) }); - while rcc.cfgr1.read().sws().bits() != 0b00 {} + rcc.cfgr1().modify(|_, w| unsafe { w.sw().bits(0b00) }); + while rcc.cfgr1().read().sws().bits() != 0b00 {} } // @@ -424,8 +424,8 @@ impl CFGR { // LSI if requested (or if we needed by LSE CSS in future) let lsi_used = if self.lsi { - rcc.bdcr.modify(|_, w| w.lsion().set_bit()); - while rcc.bdcr.read().lsirdy().bit_is_clear() {} + rcc.bdcr().modify(|_, w| w.lsion().set_bit()); + while rcc.bdcr().read().lsirdy().bit_is_clear() {} true } else { false @@ -438,45 +438,45 @@ impl CFGR { pwr.cr1.reg().modify(|_, w| w.dbp().set_bit()); // Enable LSE (bypass if set) if lse_cfg.bypass == CrystalBypass::Enable { - rcc.bdcr.modify(|_, w| w.lsebyp().set_bit()); + rcc.bdcr().modify(|_, w| w.lsebyp().set_bit()); } - rcc.bdcr.modify(|_, w| w.lseon().set_bit()); - while rcc.bdcr.read().lserdy().bit_is_clear() {} + rcc.bdcr().modify(|_, w| w.lseon().set_bit()); + while rcc.bdcr().read().lserdy().bit_is_clear() {} // Skipped: LSESYS and LSE CSS/glitch filter } // HSE if requested if let Some(hse_cfg) = &self.hse { - rcc.cr.modify(|_, w| { + rcc.cr().modify(|_, w| { if hse_cfg.bypass == CrystalBypass::Enable { w.hsebyp().set_bit(); } w.hseon().set_bit() }); - while rcc.cr.read().hserdy().bit_is_clear() {} + while rcc.cr().read().hserdy().bit_is_clear() {} if hse_cfg.css == ClockSecuritySystem::Enable { // Enable CSS on HSE (CR.CSSON) - rcc.cr.modify(|_, w| w.csson().set_bit()); + rcc.cr().modify(|_, w| w.csson().set_bit()); } } // MSI range if set explicitly if let Some(msi) = self.msi { unsafe { - rcc.icscr1.modify(|_, w| { + rcc.icscr1().modify(|_, w| { w.msirgsel().set_bit(); w.msisrange().bits(msi.to_range_bits()); w }) }; - while rcc.cr.read().msisrdy().bit_is_clear() {} + while rcc.cr().read().msisrdy().bit_is_clear() {} } // HSI48 if self.hsi48 { - rcc.cr.modify(|_, w| w.hsi48on().set_bit()); - while rcc.cr.read().hsi48rdy().bit_is_clear() {} + rcc.cr().modify(|_, w| w.hsi48on().set_bit()); + while rcc.cr().read().hsi48rdy().bit_is_clear() {} } // @@ -510,8 +510,8 @@ impl CFGR { // If we need HSI for PLL1 and it's not on, turn it on if pll_src == PllSource::HSI16 { - rcc.cr.modify(|_, w| w.hsion().set_bit()); - while rcc.cr.read().hsirdy().bit_is_clear() {} + rcc.cr().modify(|_, w| w.hsion().set_bit()); + while rcc.cr().read().hsirdy().bit_is_clear() {} } let want_sysclk = match (self.sysclk, self.msi) { @@ -604,7 +604,7 @@ impl CFGR { } // Program prescalers first (CFGR2: HPRE/PPRE1/PPRE2) - rcc.cfgr2.modify(|_, w| unsafe { + rcc.cfgr2().modify(|_, w| unsafe { w.hpre().bits(hpre_bits); w.ppre1().bits(ppre1_bits); w.ppre2().bits(ppre2_bits) @@ -623,12 +623,12 @@ impl CFGR { assert!(sysclk_calc <= 80_000_000); // Disable PLL1 before reconfig - rcc.cr.modify(|_, w| w.pll1on().clear_bit()); - while rcc.cr.read().pll1rdy().bit_is_set() {} + rcc.cr().modify(|_, w| w.pll1on().clear_bit()); + while rcc.cr().read().pll1rdy().bit_is_set() {} // Set PLL source let src_bits = pll_src.to_pllsrc_bits(); - rcc.pll1cfgr.modify(|_, w| unsafe { + rcc.pll1cfgr().modify(|_, w| unsafe { w.pll1src().bits(src_bits); // VCI range selection (very rough): 4..8 => range0, 8..16 => range1 let rge = if vco_in < 8_000_000 { 0b00 } else { 0b11 }; @@ -641,7 +641,7 @@ impl CFGR { }); // Program N, R in PLL1DIVR - rcc.pll1divr.modify(|_, w| unsafe { + rcc.pll1divr().modify(|_, w| unsafe { w.pll1n().bits((pll.n - 1) as u16); w.pll1r().bits(pll.r - 1); // Leave P/Q untouched/disabled (skipped) @@ -649,30 +649,30 @@ impl CFGR { }); // Enable PLL1 - rcc.cr.modify(|_, w| w.pll1on().set_bit()); - while rcc.cr.read().pll1rdy().bit_is_clear() {} + rcc.cr().modify(|_, w| w.pll1on().set_bit()); + while rcc.cr().read().pll1rdy().bit_is_clear() {} // Enable PLL1 R output - rcc.pll1cfgr.modify(|_, w| w.pll1ren().set_bit()); + rcc.pll1cfgr().modify(|_, w| w.pll1ren().set_bit()); // Switch SYSCLK to PLL1 (CFGR1.SW = 11) sysclk_src_bits = 0b11; - rcc.cfgr1.modify(|_, w| unsafe { w.sw().bits(sysclk_src_bits) }); + rcc.cfgr1().modify(|_, w| unsafe { w.sw().bits(sysclk_src_bits) }); } else { // Keep MSI as SYSCLK (CFGR1.SW = 00) sysclk_src_bits = 0b00; if used_msi.is_none() { used_msi = Some(MsiFreq::MSI4); } - rcc.cfgr1.modify(|_, w| unsafe { w.sw().bits(sysclk_src_bits) }); + rcc.cfgr1().modify(|_, w| unsafe { w.sw().bits(sysclk_src_bits) }); } // Wait for SWS - while rcc.cfgr1.read().sws().bits() != sysclk_src_bits {} + while rcc.cfgr1().read().sws().bits() != sysclk_src_bits {} // If we ended up on PLL, and MSI wasn't requested for other purposes, we can switch MSI off if used_msi.is_none() && sysclk_src_bits == 0b11 { - rcc.cr.modify(|_, w| w.msison().clear_bit()); + rcc.cr().modify(|_, w| w.msison().clear_bit()); } Clocks {