filipriec/stm32u575-hal
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Priec
2025-10-19 13:53:38 +02:00
parent ae298c150e
commit 7445c46052
1 changed files with 3 additions and 3 deletions
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6
src/rcc/rcc.rs
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@@ -435,7 +435,7 @@ impl CFGR {
if let Some(lse_cfg) = &self.lse { if let Some(lse_cfg) = &self.lse {
// Enable backup domain write access // Enable backup domain write access
// NOTE: depends on your Pwr wrapper; mirrors L4 HAL style // NOTE: depends on your Pwr wrapper; mirrors L4 HAL style
pwr.cr1.reg().modify(|_, w| w.dbp().set_bit()); pwr.dbpr.reg().modify(|_, w| w.dbp().set_bit());
// Enable LSE (bypass if set) // Enable LSE (bypass if set)
if lse_cfg.bypass == CrystalBypass::Enable { if lse_cfg.bypass == CrystalBypass::Enable {
rcc.bdcr().modify(|_, w| w.lsebyp().set_bit()); rcc.bdcr().modify(|_, w| w.lsebyp().set_bit());
@@ -588,7 +588,7 @@ impl CFGR {
// Adjust Flash latency (simple L4-like thresholds for <=80 MHz) // Adjust Flash latency (simple L4-like thresholds for <=80 MHz)
unsafe { unsafe {
acr.acr().write(|w| { acr.reg().write(|w| {
w.latency().bits(if hclk <= 16_000_000 { w.latency().bits(if hclk <= 16_000_000 {
0b000 0b000
} else if hclk <= 32_000_000 { } else if hclk <= 32_000_000 {
@@ -600,7 +600,7 @@ impl CFGR {
} else { } else {
0b100 0b100
}) })
}) });
} }
// Program prescalers first (CFGR2: HPRE/PPRE1/PPRE2) // Program prescalers first (CFGR2: HPRE/PPRE1/PPRE2)