we compiled

src/rcc/rcc.rs

@@ -435,7 +435,7 @@ impl CFGR {
         if let Some(lse_cfg) = &self.lse {
             // Enable backup domain write access
             // NOTE: depends on your Pwr wrapper; mirrors L4 HAL style
-            pwr.cr1.reg().modify(|_, w| w.dbp().set_bit());
+            pwr.dbpr.reg().modify(|_, w| w.dbp().set_bit());
             // Enable LSE (bypass if set)
             if lse_cfg.bypass == CrystalBypass::Enable {
                 rcc.bdcr().modify(|_, w| w.lsebyp().set_bit());
@@ -588,7 +588,7 @@ impl CFGR {
 
         // Adjust Flash latency (simple L4-like thresholds for <=80 MHz)
         unsafe {
-            acr.acr().write(|w| {
+            acr.reg().write(|w| {
                 w.latency().bits(if hclk <= 16_000_000 {
                     0b000
                 } else if hclk <= 32_000_000 {
@@ -600,7 +600,7 @@ impl CFGR {
                 } else {
                     0b100
                 })
-            })
+            });
         }
 
         // Program prescalers first (CFGR2: HPRE/PPRE1/PPRE2)