more PAC compatibility fixes

src/pwr.rs

@@ -218,7 +218,7 @@ impl PwrExt for PWR {
     fn constrain(self) -> Pwr {
         // Enable PWR clock on AHB3 (per U5 HAL: __HAL_RCC_PWR_CLK_ENABLE())
         let rcc = unsafe { &*RCC::ptr() };
-        rcc.ahb3enr.modify(|_, w| w.pwren().set_bit());
+        rcc.ahb3enr().modify(|_, w| w.pwren().set_bit());
         // Small barrier after clock enabling (mirroring typical patterns)
         cortex_m::asm::dsb();
 
@@ -239,7 +239,7 @@ pub struct CR1 {
 impl CR1 {
     #[inline(always)]
     pub(crate) fn reg(&mut self) -> &pac::pwr::CR1 {
-        unsafe { &(*PWR::ptr()).cr1 }
+        unsafe { &(*PWR::ptr()).cr1() }
     }
 }
 
@@ -250,7 +250,7 @@ pub struct WUCR1 {
 impl WUCR1 {
     #[inline(always)]
     pub(crate) fn reg(&mut self) -> &pac::pwr::WUCR1 {
-        unsafe { &(*PWR::ptr()).wucr1 }
+        unsafe { &(*PWR::ptr()).wucr1() }
     }
 }
 
@@ -261,7 +261,7 @@ pub struct WUSCR {
 impl WUSCR {
     #[inline(always)]
     pub(crate) fn reg(&mut self) -> &pac::pwr::WUSCR {
-        unsafe { &(*PWR::ptr()).wuscr }
+        unsafe { &(*PWR::ptr()).wuscr() }
     }
 }
 
@@ -272,7 +272,7 @@ pub struct WUSR {
 impl WUSR {
     #[inline(always)]
     pub(crate) fn reg(&mut self) -> &pac::pwr::WUSR {
-        unsafe { &(*PWR::ptr()).wusr }
+        unsafe { &(*PWR::ptr()).wusr() }
     }
 }
 
@@ -283,6 +283,6 @@ pub struct DBPR {
 impl DBPR {
     #[inline(always)]
     pub(crate) fn reg(&mut self) -> &pac::pwr::DBPR {
-        unsafe { &(*PWR::ptr()).dbpr }
+        unsafe { &(*PWR::ptr()).dbpr() }
     }
 }

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