59 lines
1.8 KiB
Rust
59 lines
1.8 KiB
Rust
// src/dma_timer.rs
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use embassy_stm32::{
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peripherals::{TIM6, TIM7},
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rcc,
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timer::low_level::Timer,
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Peri,
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};
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use core::mem;
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use embassy_stm32::timer::BasicInstance;
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use embassy_stm32::pac::timer::vals::Urs;
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/// Initializes TIM6 to tick at `baud * oversample` frequency.
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/// Each TIM6 update event triggers one DMA beat.
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pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
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rcc::enable_and_reset::<TIM6>();
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let ll = Timer::new(tim6);
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configure_basic_timer(&ll, baud, oversample);
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mem::forget(ll);
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}
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/// Initializes TIM7 to tick at `baud * oversample` frequency.
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/// Each TIM7 update event triggers one DMA beat.
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pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
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rcc::enable_and_reset::<TIM7>();
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let ll = Timer::new(tim7);
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configure_basic_timer(&ll, baud, oversample);
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mem::forget(ll);
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}
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// Shared internal helper — identical CR1/ARR setup
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fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
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let f_timer = rcc::frequency::<T>().0;
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let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
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// Compute ARR (prescaler = 0)
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let mut arr = (f_timer / target).saturating_sub(1) as u16;
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if arr == 0 { arr = 1; }
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ll.regs_basic().cr1().write(|w| {
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w.set_cen(false);
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w.set_opm(false);
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w.set_udis(false);
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w.set_urs(Urs::ANY_EVENT);
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});
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ll.regs_basic().psc().write_value(0u16);
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ll.regs_basic().arr().write(|w| w.set_arr(arr));
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ll.regs_basic().dier().modify(|w| w.set_ude(true));
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ll.regs_basic().egr().write(|w| w.set_ug(true));
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ll.regs_basic().cr1().write(|w| {
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w.set_opm(false);
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w.set_cen(true);
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w.set_udis(false);
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w.set_urs(Urs::ANY_EVENT);
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});
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}
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