2 Commits

Author SHA1 Message Date
Priec
0ecf821e40 moved properly 2025-10-31 13:19:54 +01:00
Priec
8de34e13d9 solution detached from main for async buffered generalized2 2025-10-31 13:00:21 +01:00
8 changed files with 124 additions and 78 deletions

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@@ -25,7 +25,7 @@ static PIPE: Pipe<CriticalSectionRawMutex, 256> = Pipe::new();
// Baud rate: one TIM6 update equals one UART bit-time // Baud rate: one TIM6 update equals one UART bit-time
const BAUD: u32 = 115_200; const BAUD: u32 = 115_200;
const TX_PIN_BIT: u8 = 2; // PA2 const TX_PIN_BIT: u8 = 2; // PA2
const OVERSAMPLE: u16 = 6; const OVERSAMPLE: u16 = 16;
const UART_CFG: UartConfig = UartConfig { const UART_CFG: UartConfig = UartConfig {
data_bits: 8, data_bits: 8,
@@ -125,7 +125,7 @@ async fn dma_tx_task(ch: Peri<'static, GPDMA1_CH0>) {
{ {
Ok(()) => {} Ok(()) => {}
Err(_) => { Err(_) => {
warn!("DMA timeout: no TIM6 request (wrong DMAMUX req?)"); warn!("DMA timeout: no TIM6 request");
dump_tim6_regs(); dump_tim6_regs();
dump_dma_ch0_regs(); dump_dma_ch0_regs();
} }

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@@ -47,5 +47,5 @@ pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16)
w.set_udis(false); w.set_udis(false);
w.set_urs(Urs::ANY_EVENT); w.set_urs(Urs::ANY_EVENT);
}); });
mem::forget(ll); mem::forget(ll); // KEEP THE TIMER ALIVE
} }

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@@ -1,93 +1,51 @@
// src/bin/main.rs // src/bin/main.rs
#![no_std] #![no_std]
#![no_main] #![no_main]
use defmt::*; use defmt::*;
use {defmt_rtt as _, panic_probe as _};
use embassy_executor::Spawner; use embassy_executor::Spawner;
use embassy_stm32::usart::{BufferedInterruptHandler, BufferedUart, Config};
use embassy_stm32::bind_interrupts; use embassy_stm32::bind_interrupts;
use embassy_stm32::peripherals; use embassy_stm32::peripherals;
use embassy_stm32::usart::{BufferedInterruptHandler, BufferedUart, Config}; use embassy_time::Instant;
use embedded_io_async::{Read, Write};
use embassy_time::{Timer, Duration, Instant};
use static_cell::StaticCell; use static_cell::StaticCell;
use embassy_futures::yield_now;
use {defmt_rtt as _, panic_probe as _};
use embassy_futures::select::{select, Either};
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
use async_uart::safety::{preflight_and_suggest_yield_period, RX_PIPE_CAP, TX_PIPE_CAP};
static UART_TX: Pipe<CriticalSectionRawMutex, TX_PIPE_CAP> = Pipe::new(); use async_uart::uart::usart1;
static UART_RX: Pipe<CriticalSectionRawMutex, RX_PIPE_CAP> = Pipe::new();
bind_interrupts!( bind_interrupts!(struct Irqs {
struct Irqs {
USART1 => BufferedInterruptHandler<peripherals::USART1>; USART1 => BufferedInterruptHandler<peripherals::USART1>;
} });
);
#[embassy_executor::task]
async fn uart_task(mut uart: BufferedUart<'static>) {
let mut rx_byte = [0u8; 1];
let mut tx_buf = [0u8; 64];
loop {
// Wait for either RX or TX events.
let rx_fut = uart.read(&mut rx_byte);
let tx_fut = async {
// Until there's outgoing data in TX pipe
let n = UART_TX.read(&mut tx_buf).await;
n
};
match select(rx_fut, tx_fut).await {
// Incoming data from UART hardware
Either::First(res) => {
if let Ok(_) = res {
// Forward to RX pipe
let _ = UART_RX.write(&rx_byte).await;
let _ = UART_TX.try_write(&rx_byte);
}
}
// Outgoing data waiting in TX pipe
Either::Second(n) => {
unwrap!(uart.write(&tx_buf[..n]).await);
}
}
}
}
#[embassy_executor::main] #[embassy_executor::main]
async fn main(spawner: Spawner) { async fn main(spawner: Spawner) {
info!("tititititi"); info!("boot");
let p = embassy_stm32::init(Default::default()); let p = embassy_stm32::init(Default::default());
static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
let tx_buf = TX_BUF.init([0; 256]);
let rx_buf = RX_BUF.init([0; 256]);
let mut cfg = Config::default(); let mut cfg = Config::default();
cfg.baudrate = 230_400; cfg.baudrate = 230_400;
// Call preflight and get the computed yield period static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
let yield_period = preflight_and_suggest_yield_period(cfg.baudrate); static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
let usart = BufferedUart::new( let uart =
BufferedUart::new(
p.USART1, p.USART1,
p.PA10, // RX p.PA10,
p.PA9, // TX p.PA9,
tx_buf, TX_BUF.init([0; 256]),
rx_buf, RX_BUF.init([0; 256]),
Irqs, Irqs,
cfg, cfg,
).unwrap(); ).unwrap();
info!("starting uart task"); let handle = usart1::setup_and_spawn(&spawner, uart, cfg.baudrate);
spawner.spawn(uart_task(usart)).unwrap();
let mut counter: u32 = 0;
let mut rx_buf = [0u8; 64]; let mut rx_buf = [0u8; 64];
let mut last_yield = Instant::now(); let mut last_yield = Instant::now();
loop { loop {
counter = counter.wrapping_add(1); if let Ok(n) = handle.rx.try_read(&mut rx_buf) {
// Poll RX pipe for new data (non-blocking)
if let Ok(n) = UART_RX.try_read(&mut rx_buf) {
if n > 0 { if n > 0 {
if let Ok(s) = core::str::from_utf8(&rx_buf[..n]) { if let Ok(s) = core::str::from_utf8(&rx_buf[..n]) {
info!("RX got: {}", s); info!("RX got: {}", s);
@@ -97,13 +55,9 @@ async fn main(spawner: Spawner) {
} }
} }
// Guaranteed to yield before ISR RX buffer can overflow if Instant::now().duration_since(last_yield) >= handle.yield_period {
if Instant::now().duration_since(last_yield) >= yield_period { embassy_futures::yield_now().await;
yield_now().await;
last_yield = Instant::now(); last_yield = Instant::now();
// info!("Yield mf {}", counter); }
}
// Timer::after(Duration::from_micros(1)).await;
// Timer::after(Duration::from_secs(5)).await;
} }
} }

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@@ -1,2 +1,2 @@
#![no_std] #![no_std]
pub mod safety; pub mod uart;

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@@ -0,0 +1,65 @@
// src/uart/driver.rs
use defmt::unwrap;
use embassy_executor::Spawner;
use embassy_futures::select::{select, Either};
use embassy_stm32::usart::BufferedUart;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
use embassy_time::Duration;
use embedded_io_async::{Read, Write};
use crate::uart::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
pub struct UartHandle {
pub tx: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
pub rx: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
pub yield_period: Duration,
}
#[embassy_executor::task]
pub async fn uart_task(
mut uart: BufferedUart<'static>,
tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
) {
let mut rx_byte = [0u8; 1];
let mut tx_buf = [0u8; 64];
loop {
let rx_fut = uart.read(&mut rx_byte);
let tx_fut = async {
let n = tx_pipe.read(&mut tx_buf).await;
n
};
match select(rx_fut, tx_fut).await {
// Incoming data from UART hardware
Either::First(res) => {
if let Ok(_) = res {
// Forward to RX pipe and echo to TX pipe (same behavior as before)
let _ = rx_pipe.write(&rx_byte).await;
let _ = tx_pipe.try_write(&rx_byte);
}
}
// Outgoing data waiting in TX pipe
Either::Second(n) => {
unwrap!(uart.write(&tx_buf[..n]).await);
}
}
}
}
pub fn spawn_for(
spawner: &Spawner,
uart: BufferedUart<'static>,
tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
yield_period: Duration,
) -> UartHandle {
spawner.spawn(uart_task(uart, tx_pipe, rx_pipe)).unwrap();
UartHandle {
tx: tx_pipe,
rx: rx_pipe,
yield_period,
}
}

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@@ -0,0 +1,4 @@
// src/uart/mod.rs
pub mod driver;
pub mod usart1;
pub mod safety;

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@@ -0,0 +1,23 @@
// src/uart/usart1.rs
use defmt::info;
use embassy_executor::Spawner;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
use embassy_time::Duration;
use crate::uart::safety::{preflight_and_suggest_yield_period, RX_PIPE_CAP, TX_PIPE_CAP};
use crate::uart::driver::{spawn_for, UartHandle};
// Static pipes and buffers
static UART1_TX_PIPE: Pipe<CriticalSectionRawMutex, TX_PIPE_CAP> = Pipe::new();
static UART1_RX_PIPE: Pipe<CriticalSectionRawMutex, RX_PIPE_CAP> = Pipe::new();
pub fn setup_and_spawn(
spawner: &Spawner,
uart: embassy_stm32::usart::BufferedUart<'static>,
baudrate: u32,
) -> UartHandle {
let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
info!("USART1 initialized");
spawn_for(spawner, uart, &UART1_TX_PIPE, &UART1_RX_PIPE, yield_period)
}