working, but data are in pipe, but we read ringbuffer, critical bug, fix now

dma_gpio/src/software_uart/runtime.rs

@@ -1,18 +1,18 @@
 // src/software_uart/runtime.rs
-use defmt::{info, warn};
 use embassy_executor::task;
+use embassy_stm32::pac::GPIOA;
 use embassy_stm32::{
-    dma::{ReadableRingBuffer as DmaRingRx, TransferOptions},
     peripherals::{GPDMA1_CH0, GPDMA1_CH1},
     Peri,
 };
-use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
-use embassy_time::Duration;
-use crate::software_uart::{
-    gpio_dma_uart_rx::TIM7_UP_REQ,
-    gpio_dma_uart_tx::GpioDmaBsrrTx,
-    debug::{dump_dma_ch0_regs, dump_tim6_regs},
+use embassy_stm32::dma::{
+    ReadableRingBuffer as DmaRingRx,
+    WritableRingBuffer as DmaRingTx,
+    TransferOptions,
 };
+use crate::software_uart::gpio_dma_uart_tx::TIM6_UP_REQ;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use crate::software_uart::gpio_dma_uart_rx::TIM7_UP_REQ;
 
 /// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
 #[task]
@@ -38,32 +38,28 @@ pub async fn rx_dma_task(
     }
 }
 
-/// TX DMA task: dequeues prebuilt frames from PIPE_TX and writes to GPIOA.BSRR
+/// TX DMA ring task: streams u32 BSRR words paced by TIM6.
 #[task]
 pub async fn tx_dma_task(
     ch: Peri<'static, GPDMA1_CH0>,
-    pipe_tx: &'static Pipe<CriticalSectionRawMutex, 256>,
+    ring_mem: &'static mut [u32],
 ) {
-    let mut tx = GpioDmaBsrrTx::new(ch);
-    info!("DMA TX task started");
+    let bsrr_ptr = GPIOA.bsrr().as_ptr() as *mut u32;
 
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring_mem is exclusive here, bsrr_ptr valid, paced by TIM6
+    let mut tx = unsafe {
+        DmaRingTx::<u32>::new(ch, TIM6_UP_REQ, bsrr_ptr, ring_mem, opts)
+    };
+    
+    tx.start();
+    defmt::info!("TX DMA ring started");
+
+    // The DMA now streams ring_mem.
     loop {
-        let mut b = [0u8; 4];
-        let n = pipe_tx.read(&mut b).await;
-        if n != 4 {
-            continue;
-        }
-
-        let w = u32::from_le_bytes(b);
-        info!("DMA write 0x{:08X} -> GPIOA.BSRR", w);
-
-        match embassy_time::with_timeout(Duration::from_millis(20), tx.write_word(w)).await {
-            Ok(()) => {}
-            Err(_) => {
-                warn!("DMA timeout: no TIM6 request");
-                dump_tim6_regs();
-                dump_dma_ch0_regs();
-            }
-        }
+        // embassy_futures::yield_now().await;
     }
 }