Tx only does not work

dma_gpio2/src/bin/main.rs

@@ -0,0 +1,102 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_futures::yield_now;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_time::{Duration, Timer};
+use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
+use dma_gpio::software_uart::{
+    dma_timer::init_tim6_for_uart,
+    gpio_dma_uart_tx::encode_uart_frames,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, TX_PIN_BIT, RX_OVERSAMPLE, TX_OVERSAMPLE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
+
+// kapitola 17.4.11 - 2 casovace pre 2 DMA
+pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
+
+static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+
+use core::future::poll_fn;
+use core::task::Poll;
+
+async fn wait_for_space<'a, W: embassy_stm32::dma::word::Word>(
+    ring: &mut embassy_stm32::dma::WritableRingBuffer<'a, W>,
+    min_free: usize,
+) {
+    poll_fn(|cx| {
+        let used = ring.len().unwrap_or(0);
+        let cap = ring.capacity();
+        if cap - used > min_free {
+            Poll::Ready(())
+        } else {
+            ring.set_waker(cx.waker());
+            Poll::Pending
+        }
+    }).await
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hehe");
+
+    let _rx = Input::new(p.PA3, Pull::Up);
+    let _tx = Output::new(p.PA2, Level::High, Speed::VeryHigh);
+
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    dump_tim6_regs();
+
+    // Safe one-time init from StaticCell
+    let tx_ring_mem: &mut [u32; TX_RING_BYTES] = TX_RING.init([0; TX_RING_BYTES]);
+
+    // Create and start the TX DMA ring in main.
+    // let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
+    let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    // SAFETY: tx_ring_mem is exclusive
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            p.GPDMA1_CH0,
+            TIM6_UP_REQ,
+            odr_ptr,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+    // Start DMA
+    tx_ring.start();
+    info!("TX DMA ring started");
+
+    let mut frame_buf = [0u32; 4096];
+
+    loop {
+        info!("tick start");
+        Timer::after(Duration::from_millis(400)).await;
+        info!("tick end");
+
+        let used = encode_uart_frames(TX_PIN_BIT, b"Hello marshmallow\r\n", &mut frame_buf).await;
+
+        // Wait for DMA to free space, async style
+        wait_for_space(&mut tx_ring, used / 2).await;
+
+        if let Err(e) = tx_ring.write_exact(&frame_buf[..used]).await {
+            warn!("DMA ring write error: {:?}", e);
+        } else {
+            info!("Frame queued to DMA ring");
+        }
+
+        yield_now().await;
+    }
+}