Tx only does not work

dma_gpio2/src/bin/main.rs

@@ -0,0 +1,102 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_futures::yield_now;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_time::{Duration, Timer};
+use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
+use dma_gpio::software_uart::{
+    dma_timer::init_tim6_for_uart,
+    gpio_dma_uart_tx::encode_uart_frames,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, TX_PIN_BIT, RX_OVERSAMPLE, TX_OVERSAMPLE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
+
+// kapitola 17.4.11 - 2 casovace pre 2 DMA
+pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
+
+static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+
+use core::future::poll_fn;
+use core::task::Poll;
+
+async fn wait_for_space<'a, W: embassy_stm32::dma::word::Word>(
+    ring: &mut embassy_stm32::dma::WritableRingBuffer<'a, W>,
+    min_free: usize,
+) {
+    poll_fn(|cx| {
+        let used = ring.len().unwrap_or(0);
+        let cap = ring.capacity();
+        if cap - used > min_free {
+            Poll::Ready(())
+        } else {
+            ring.set_waker(cx.waker());
+            Poll::Pending
+        }
+    }).await
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hehe");
+
+    let _rx = Input::new(p.PA3, Pull::Up);
+    let _tx = Output::new(p.PA2, Level::High, Speed::VeryHigh);
+
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    dump_tim6_regs();
+
+    // Safe one-time init from StaticCell
+    let tx_ring_mem: &mut [u32; TX_RING_BYTES] = TX_RING.init([0; TX_RING_BYTES]);
+
+    // Create and start the TX DMA ring in main.
+    // let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
+    let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    // SAFETY: tx_ring_mem is exclusive
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            p.GPDMA1_CH0,
+            TIM6_UP_REQ,
+            odr_ptr,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+    // Start DMA
+    tx_ring.start();
+    info!("TX DMA ring started");
+
+    let mut frame_buf = [0u32; 4096];
+
+    loop {
+        info!("tick start");
+        Timer::after(Duration::from_millis(400)).await;
+        info!("tick end");
+
+        let used = encode_uart_frames(TX_PIN_BIT, b"Hello marshmallow\r\n", &mut frame_buf).await;
+
+        // Wait for DMA to free space, async style
+        wait_for_space(&mut tx_ring, used / 2).await;
+
+        if let Err(e) = tx_ring.write_exact(&frame_buf[..used]).await {
+            warn!("DMA ring write error: {:?}", e);
+        } else {
+            info!("Frame queued to DMA ring");
+        }
+
+        yield_now().await;
+    }
+}

dma_gpio2/src/config.rs

@@ -0,0 +1,16 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+
+pub const BAUD: u32 = 9_600;
+pub const TX_PIN_BIT: u8 = 2; // PA2
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 16;
+pub const RX_RING_BYTES: usize = 4096;
+pub const TX_RING_BYTES: usize = 4096;
+pub const PIPE_RX_SIZE: usize = 256;
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};

dma_gpio2/src/lib.rs

@@ -0,0 +1,4 @@
+#![no_std]
+
+pub mod software_uart;
+pub mod config;

dma_gpio2/src/software_uart/debug.rs

@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}

dma_gpio2/src/software_uart/dma_timer.rs

@@ -0,0 +1,49 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::TIM6,
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}

dma_gpio2/src/software_uart/gpio_dma_uart_tx.rs

@@ -0,0 +1,27 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_futures::yield_now;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+use crate::config::UART_CFG;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
+    }
+    offset
+}

dma_gpio2/src/software_uart/mod.rs

@@ -0,0 +1,11 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;

dma_gpio2/src/software_uart/uart_emulation.rs

@@ -0,0 +1,151 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    let set_low = |bit: u8| -> u32 { 0 };
+    // let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> heapless::Vec<u8, 256> {
+
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+
+    while idx + (oversample as usize * (nbits + 3)) < samples.len() {
+        // Wait for start bit (falling edge: high -> low)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to middle of start bit
+            idx += (oversample / 2) as usize;
+
+            // Sanity check start bit really low
+            if samples.get(idx).copied().unwrap_or(1) != 0 {
+                idx += 1;
+                continue;
+            }
+
+            // Sample data bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                idx += oversample as usize;
+                let bit_val = samples
+                    .get(idx)
+                    .map(|&b| if b != 0 { 1u8 } else { 0u8 })
+                    .unwrap_or(1);
+                data |= bit_val << bit;
+            }
+
+            // Parity: skip / verify
+            match cfg.parity {
+                Parity::None => {}
+                Parity::Even | Parity::Odd => {
+                    idx += oversample as usize;
+                    // You can optionally add parity check here if needed
+                }
+            }
+
+            // Move past stop bits
+            let stop_skip = match cfg.stop_bits {
+                StopBits::One => oversample as usize,
+                StopBits::Two => (oversample * 2) as usize,
+            };
+            idx += stop_skip;
+
+            // Push decoded byte
+            let _ = out.push(data);
+        } else {
+            idx += 1;
+        }
+    }
+
+    out
+}