diff --git a/semestralka_1_final_crate/software_uart/src/gpio_dma_uart_rx.rs b/semestralka_1_final_crate/software_uart/src/gpio_dma_uart_rx.rs
index 52536a2..e27a4aa 100644
--- a/semestralka_1_final_crate/software_uart/src/gpio_dma_uart_rx.rs
+++ b/semestralka_1_final_crate/software_uart/src/gpio_dma_uart_rx.rs
@@ -1,4 +1,5 @@
 // src/runtime.rs
+
 use embassy_executor::task;
 use embassy_stm32::{
     dma::Request,
@@ -34,7 +35,15 @@ pub async fn rx_dma_task(
     opts.complete_transfer_ir = true;
 
     // SAFETY: ring is exclusive to this task
-    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, register, ring, opts) };
+    let mut rx = unsafe {
+        ReadableRingBuffer::new(
+            ch,
+            TIM7_UP_REQ,
+            register,
+            ring,
+            opts
+        )
+    };
     rx.start();
 
     // We read into the second half of a buffer, keeping "leftovers" in the first half.
diff --git a/semestralka_1_final_crate/software_uart/src/gpio_dma_uart_tx.rs b/semestralka_1_final_crate/software_uart/src/gpio_dma_uart_tx.rs
index e0099ed..e259eb1 100644
--- a/semestralka_1_final_crate/software_uart/src/gpio_dma_uart_tx.rs
+++ b/semestralka_1_final_crate/software_uart/src/gpio_dma_uart_tx.rs
@@ -19,8 +19,10 @@ pub async fn encode_uart_frames<'a>(
     pin_bit: u8,
     bytes: &[u8],
     out_buf: &'a mut [u32],
-    uart_cfg: &UartConfig,
+    uart_cfg: &mut UartConfig,
 ) -> usize {
+    uart_cfg.validity_check(); // clamping to min 5 bits
+
     let mut offset = 0;
     for &b in bytes {
         let mut frame = [0u32; 12];
@@ -45,7 +47,7 @@ pub async fn tx_dma_task(
     _tx_ring_mem: &'static mut [u32],
     pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
     tx_pin_bit: u8,
-    uart_cfg: &'static UartConfig,
+    uart_cfg: &'static mut UartConfig,
 ) {
     info!("TX DMA task ready (One‑shot)");
 
diff --git a/semestralka_1_final_crate/software_uart/src/uart_emulation.rs b/semestralka_1_final_crate/software_uart/src/uart_emulation.rs
index aedd321..36eb5c3 100644
--- a/semestralka_1_final_crate/software_uart/src/uart_emulation.rs
+++ b/semestralka_1_final_crate/software_uart/src/uart_emulation.rs
@@ -31,6 +31,18 @@ impl Default for UartConfig {
     }
 }
 
+impl UartConfig {
+    pub fn validity_check(&mut self) {
+        if self.data_bits < 5 {
+            defmt::warn!(
+                "Invalid UART data_bits={} – clamping to minimum 5 bits.",
+                self.data_bits
+            );
+            self.data_bits = 5;
+        }
+    }
+}
+
 /// Encodes one byte into a sequence of GPIO BSRR words
 pub fn encode_uart_byte_cfg(
     pin_bit: u8,
@@ -43,6 +55,7 @@ pub fn encode_uart_byte_cfg(
     // let set_low = |bit: u8| -> u32 { 0 }; // ODR
     let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
 
+    let nbits = cfg.data_bits;
     let mut idx = 0usize;
 
     // START bit (LOW)
@@ -50,7 +63,6 @@ pub fn encode_uart_byte_cfg(
     idx += 1;
 
     // Data bits, LSB-first
-    let nbits = cfg.data_bits.clamp(5, 8);
     for i in 0..nbits {
         let one = ((data >> i) & 1) != 0;
         out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
@@ -79,8 +91,8 @@ pub fn encode_uart_byte_cfg(
 
     // STOP bits (HIGH)
     let stop_ticks = match cfg.stop_bits {
-        StopBits::One => 1usize,
-        StopBits::Two => 2usize,
+        StopBits::One => 1,
+        StopBits::Two => 2,
     };
     for _ in 0..stop_ticks {
         out[idx] = set_high(pin_bit);