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1d needs to be builded again from scratch

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This commit is contained in:
Priec
2025-11-19 12:51:45 +01:00
parent b339b34e4d
commit da2f011682
4 changed files with 43 additions and 105 deletions
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8
semestralka_1_2hwuart_internal/Cargo.lock generated
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@@ -1064,17 +1064,17 @@ dependencies = [
[[package]]
name = "stm32-fmc"
version = "0.4.0"
version = "0.3.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "72692594faa67f052e5e06dd34460951c21e83bc55de4feb8d2666e2f15480a2"
checksum = "c7f0639399e2307c2446c54d91d4f1596343a1e1d5cab605b9cce11d0ab3858c"
dependencies = [
"embedded-hal 1.0.0",
"embedded-hal 0.2.7",
]
[[package]]
name = "stm32-metapac"
version = "18.0.0"
source = "git+https://github.com/embassy-rs/stm32-data-generated?tag=stm32-data-22374e3344a2c9150b9b3d4da45c03f398fdc54e#31546499ddabe97044beae13ca8b535575b52a56"
source = "git+https://github.com/embassy-rs/stm32-data-generated?tag=stm32-data-b9f6b0c542d85ee695d71c35ced195e0cef51ac0#9b8fb67703361e2237b6c1ec4f1ee5949223d412"
dependencies = [
"cortex-m",
"cortex-m-rt",

24
semestralka_1_2hwuart_internal/src/bin/main.rs
View File

@@ -111,9 +111,7 @@ async fn main(spawner: Spawner) {
let mut last_state: u8 = 0;
loop {
tx_pin.set_high();
Timer::after(Duration::from_millis(10)).await;
info!("tick start");
// info!("tick start");
// Timer::after(Duration::from_millis(100)).await;
// info!("tick end");
@@ -125,24 +123,6 @@ async fn main(spawner: Spawner) {
// }
// yield_now().await;
let bit = rx_pin.is_high();
// info!("Rx_pin read (high): {}", bit);
if bit as u8 != last_state {
info!(
"SW RX -> PD6 changed, new state = {}",
if bit { "HIGH" } else { "LOW" }
);
last_state = bit as u8;
continue;
yield_now().await;
}
Timer::after(Duration::from_millis(1)).await;
// ZNOVA TO ISTE ALE LOW
tx_pin.set_low();
Timer::after(Duration::from_millis(1)).await;
let low_state = rx_pin.is_high();
defmt::info!("Rx_pin (read): {}", low_state);
yield_now().await;
}
@@ -174,7 +154,7 @@ pub async fn bridge_usart2_rx_to_usart1_tx(
let n = usart2_rx.read(&mut buf).await;
if n > 0 {
let _ = usart1_tx.write(&buf[..n]).await;
info!("bridge: USART2 -> USART1 sent {} bytes", n);
// info!("bridge: USART2 -> USART1 sent {} bytes", n);
}
yield_now().await;
}