filipriec/stm32_rust
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

toggle in the interrupt is working

Browse Source
This commit is contained in:
Priec
2025-11-19 11:39:55 +01:00
parent 7a8a308620
commit c5bee53a30
3 changed files with 45 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
semestralka_1g_empty_toggle/Cargo.lock generated
View File

@@ -1064,17 +1064,17 @@ dependencies = [
[[package]]
name = "stm32-fmc"
version = "0.4.0"
version = "0.3.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "72692594faa67f052e5e06dd34460951c21e83bc55de4feb8d2666e2f15480a2"
checksum = "c7f0639399e2307c2446c54d91d4f1596343a1e1d5cab605b9cce11d0ab3858c"
dependencies = [
"embedded-hal 1.0.0",
"embedded-hal 0.2.7",
]
[[package]]
name = "stm32-metapac"
version = "18.0.0"
source = "git+https://github.com/embassy-rs/stm32-data-generated?tag=stm32-data-22374e3344a2c9150b9b3d4da45c03f398fdc54e#31546499ddabe97044beae13ca8b535575b52a56"
source = "git+https://github.com/embassy-rs/stm32-data-generated?tag=stm32-data-b9f6b0c542d85ee695d71c35ced195e0cef51ac0#9b8fb67703361e2237b6c1ec4f1ee5949223d412"
dependencies = [
"cortex-m",
"cortex-m-rt",

96
semestralka_1g_empty_toggle/src/bin/main.rs
View File

@@ -9,27 +9,26 @@ use embassy_stm32::dma::Request;
use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
use dma_gpio::software_uart::{
dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
gpio_dma_uart_rx::rx_dma_task,
debug::dump_tim6_regs,
};
use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES};
use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
use static_cell::StaticCell;
use embassy_futures::yield_now;
use dma_gpio::hw_uart_pc::usart1;
use dma_gpio::hw_uart_pc::driver::uart_task;
use embassy_stm32::usart::{BufferedUart, Config, BufferedInterruptHandler};
use embassy_stm32::peripherals;
use embassy_stm32::bind_interrupts;
use dma_gpio::config::{PIPE_HW_TX, PIPE_HW_RX, PIPE_SW_TX, PIPE_SW_RX};
use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
use dma_gpio::hw_uart_internal::usart2;
use dma_gpio::hw_uart_internal::driver::uart_task as uart_task_internal;
use dma_gpio::config::{PIPE_INT_TX, PIPE_INT_RX};
use embassy_stm32::pac;
use embassy_stm32::interrupt;
use embassy_time::{Duration, Timer};
use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, channel::Channel};
use core::cell::RefCell;
use cortex_m::interrupt::Mutex;
use {defmt_rtt as _, panic_probe as _};
static RAW_BITS_CHANNEL: Channel<CriticalSectionRawMutex, u8, 1024> = Channel::new();
// ** NEW GLOBAL for TX pin (PB0) **
static TX_PIN_GLOBAL: Mutex<RefCell<Option<&'static mut Output<'static>>>> =
Mutex::new(RefCell::new(None));
// Software uart
pub const TIM6_UP_REQ: Request = 4;
static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
@@ -41,71 +40,46 @@ async fn main(spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("init m8");
// SOFTWARE UART
let rx_pin = Input::new(p.PD6, Pull::Up);
// Configure TX as output (PB0)
let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
// ** make tx_pin global so ISR can use it **
use cortex_m::interrupt::free;
let tx_pin_ref: &'static mut Output<'static> = unsafe { core::mem::transmute(&mut tx_pin) };
free(|cs| TX_PIN_GLOBAL.borrow(cs).replace(Some(tx_pin_ref)));
init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
dump_tim6_regs();
// EDN OF SOFTWARE UART
unsafe { cortex_m::peripheral::NVIC::unmask(pac::Interrupt::TIM7) };
let mut last_yield = Instant::now();
let mut buf = [0u8; 32];
let mut last_state: u8 = 0;
loop {
tx_pin.set_high();
Timer::after(Duration::from_millis(100)).await;
info!("tick start");
// Timer::after(Duration::from_millis(100)).await;
// info!("tick end");
// let n1 = PIPE_HW_RX.read(&mut buf).await;
// if n1 > 0 {
// info!("PC received: {:a}", &buf[..n1]);
// let _ = PIPE_SW_TX.write(&buf[..n1]).await;
// info!("SW UART TX sent echo: {:a}", &buf[..n1]);
// }
// yield_now().await;
// info!("Rx_pin read (high): {}", bit);
// ZNOVA TO ISTE ALE LOW
tx_pin.set_low();
Timer::after(Duration::from_millis(1)).await;
yield_now().await;
}
}
#[embassy_executor::task]
pub async fn bridge_usart1_rx_to_usart2_tx(
usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
) {
let mut buf = [0u8; 64];
loop {
let n = usart1_rx.read(&mut buf).await;
if n > 0 {
let _ = usart2_tx.write(&buf[..n]).await;
info!("bridge: USART1 -> USART2 sent {} bytes", n);
}
}
}
#[interrupt]
fn TIM7() {
let tim = unsafe { pac::TIM7 };
if tim.sr().read().uif() {
tim.sr().modify(|w| w.set_uif(false));
#[embassy_executor::task]
pub async fn bridge_usart2_rx_to_usart1_tx(
usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
) {
let mut buf = [0u8; 64];
loop {
let n = usart2_rx.read(&mut buf).await;
if n > 0 {
let _ = usart1_tx.write(&buf[..n]).await;
info!("bridge: USART2 -> USART1 sent {} bytes", n);
}
cortex_m::interrupt::free(|cs| {
if let Some(pin) = TX_PIN_GLOBAL.borrow(cs).borrow_mut().as_mut() {
pin.toggle();
if pin.is_set_high() {
info!("1");
} else {
info!("0");
}
}
});
}
}

5
semestralka_1g_empty_toggle/src/software_uart/dma_timer.rs
View File

@@ -25,6 +25,8 @@ pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16)
rcc::enable_and_reset::<TIM7>();
let ll = Timer::new(tim7);
configure_basic_timer(&ll, baud, oversample);
// Enable Update Interrupt (UIE)
ll.regs_basic().dier().modify(|w| w.set_uie(true));
mem::forget(ll);
}
@@ -49,6 +51,9 @@ fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversam
ll.regs_basic().dier().modify(|w| w.set_ude(true));
ll.regs_basic().egr().write(|w| w.set_ug(true));
// Clear spurious UIF from UG trigger
ll.regs_basic().sr().modify(|w| w.set_uif(false));
ll.regs_basic().cr1().write(|w| {
w.set_opm(false);
w.set_cen(true);