not working interrupt via tim7 to read data

semestralka_1d_rx_bez_dma/src/software_uart/dma_timer.rs

@@ -1,4 +1,4 @@
-// src/dma_timer.rs
+// src/software_uart/dma_timer.rs
 
 use embassy_stm32::{
     peripherals::{TIM6, TIM7},
@@ -20,11 +20,19 @@ pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16)
 }
 
 /// Initializes TIM7 to tick at `baud * oversample` frequency.
-/// Each TIM7 update event triggers one DMA beat.
+/// Each TIM7 update event triggers one DMA beat AND an Interrupt.
 pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
     rcc::enable_and_reset::<TIM7>();
     let ll = Timer::new(tim7);
+    
+    // Reuse the common config first
     configure_basic_timer(&ll, baud, oversample);
+
+    // Enable Update Interrupt (UIE) specifically for TIM7
+    ll.regs_basic().dier().modify(|w| {
+        w.set_uie(true);
+    });
+    
     mem::forget(ll);
 }
 
@@ -46,7 +54,9 @@ fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversam
 
     ll.regs_basic().psc().write_value(0u16);
     ll.regs_basic().arr().write(|w| w.set_arr(arr));
-    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    
+    ll.regs_basic().dier().modify(|w| w.set_ude(true)); 
+    
     ll.regs_basic().egr().write(|w| w.set_ug(true));
 
     ll.regs_basic().cr1().write(|w| {