redesigned, removed redundancy
This commit is contained in:
@@ -12,7 +12,7 @@ use dma_gpio::software_uart::{
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gpio_dma_uart_tx::{
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write_uart_frames_to_ring, Parity, StopBits, UartConfig, TIM6_UP_REQ,
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},
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runtime::rx_dma_task,
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gpio_dma_uart_rx::rx_dma_task,
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debug::dump_tim6_regs,
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};
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use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
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@@ -1,57 +1,39 @@
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// src/gpio_dma_uart_rx.rs
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// src/software_uart/runtime.rs
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use embassy_executor::task;
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use embassy_stm32::{
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dma::{Request, Transfer, TransferOptions},
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dma::Request,
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peripherals::GPDMA1_CH1,
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Peri,
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};
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use embassy_stm32::dma::{
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ReadableRingBuffer as DmaRingRx,
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TransferOptions,
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};
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use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
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// RM0456 tabulka 137
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// datasheet tabulka 137
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pub const TIM7_UP_REQ: Request = 5;
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pub struct GpioDmaRx<'d, const N: usize> {
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ch: Peri<'d, GPDMA1_CH1>,
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pin_bit: u8,
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buf: &'d mut [u32; N],
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opts: TransferOptions,
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pipe_rx: &'d Pipe<CriticalSectionRawMutex, 256>,
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}
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/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
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#[task]
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pub async fn rx_dma_task(
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ch: Peri<'static, GPDMA1_CH1>,
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pipe_rx: &'static Pipe<CriticalSectionRawMutex, 256>,
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ring: &'static mut [u8],
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) {
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let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
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impl<'d, const N: usize> GpioDmaRx<'d, N> {
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pub fn new(
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ch: Peri<'d, GPDMA1_CH1>,
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pin_bit: u8,
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buf: &'d mut [u32; N],
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pipe_rx: &'d Pipe<CriticalSectionRawMutex, 256>,
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) -> Self {
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Self {
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ch,
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pin_bit,
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buf,
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opts: TransferOptions::default(),
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pipe_rx,
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}
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}
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let mut opts = TransferOptions::default();
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opts.half_transfer_ir = true;
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opts.complete_transfer_ir = true;
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pub async fn run(&mut self) -> ! {
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loop {
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let gpioa_idr_addr = embassy_stm32::pac::GPIOA.as_ptr() as *mut u32;
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// SAFETY: ring is exclusive to this task
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let mut rx = unsafe { DmaRingRx::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
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rx.start();
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unsafe {
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Transfer::new_read(
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self.ch.reborrow(),
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TIM7_UP_REQ,
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gpioa_idr_addr,
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&mut self.buf[..],
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self.opts,
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)
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}
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.await;
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for &word in self.buf.iter() {
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let bit_high = ((word >> self.pin_bit) & 1) as u8;
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self.pipe_rx.write(&[bit_high]).await;
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}
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}
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let mut chunk = [0u8; 256];
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loop {
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let _ = rx.read_exact(&mut chunk).await;
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pipe_rx.write(&chunk).await;
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}
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}
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@@ -3,11 +3,9 @@
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pub mod gpio_dma_uart_tx;
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pub mod gpio_dma_uart_rx;
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pub mod dma_timer;
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pub mod runtime;
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pub mod debug;
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pub use gpio_dma_uart_tx::*;
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pub use gpio_dma_uart_rx::*;
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pub use dma_timer::*;
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pub use runtime::*;
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pub use debug::*;
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@@ -1,36 +0,0 @@
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// src/software_uart/runtime.rs
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use embassy_executor::task;
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use embassy_stm32::{
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peripherals::GPDMA1_CH1,
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Peri,
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};
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use embassy_stm32::dma::{
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ReadableRingBuffer as DmaRingRx,
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TransferOptions,
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};
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use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
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use crate::software_uart::gpio_dma_uart_rx::TIM7_UP_REQ;
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/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
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#[task]
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pub async fn rx_dma_task(
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ch: Peri<'static, GPDMA1_CH1>,
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pipe_rx: &'static Pipe<CriticalSectionRawMutex, 256>,
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ring: &'static mut [u8],
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) {
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let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
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let mut opts = TransferOptions::default();
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opts.half_transfer_ir = true;
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opts.complete_transfer_ir = true;
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// SAFETY: ring is exclusive to this task
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let mut rx = unsafe { DmaRingRx::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
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rx.start();
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let mut chunk = [0u8; 256];
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loop {
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let _ = rx.read_exact(&mut chunk).await;
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pipe_rx.write(&chunk).await;
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}
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}
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