filipriec/stm32_rust
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not working, i have no clue why

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This commit is contained in:
Priec
2025-11-05 23:40:59 +01:00
parent f2fda10c7a
commit 9358f2e8ec
3 changed files with 28 additions and 29 deletions
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52
dma_gpio2/src/bin/main.rs
View File

@@ -17,33 +17,16 @@ use dma_gpio::software_uart::{
};
use dma_gpio::config::{BAUD, TX_PIN_BIT, RX_OVERSAMPLE, TX_OVERSAMPLE};
use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
use dma_gpio::software_uart::dump_dma_ch0_regs;
use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _};
// kapitola 17.4.11 - 2 casovace pre 2 DMA
pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
// pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
pub const TIM6_UP_REQ: u8 = 4;
static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
use core::future::poll_fn;
use core::task::Poll;
async fn wait_for_space<'a, W: embassy_stm32::dma::word::Word>(
ring: &mut embassy_stm32::dma::WritableRingBuffer<'a, W>,
min_free: usize,
) {
poll_fn(|cx| {
let used = ring.len().unwrap_or(0);
let cap = ring.capacity();
if cap - used > min_free {
Poll::Ready(())
} else {
ring.set_waker(cx.waker());
Poll::Pending
}
}).await
}
#[embassy_executor::main]
async fn main(spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
@@ -58,6 +41,11 @@ async fn main(spawner: Spawner) {
// Safe one-time init from StaticCell
let tx_ring_mem: &mut [u32; TX_RING_BYTES] = TX_RING.init([0; TX_RING_BYTES]);
let pin_mask = 1u32 << TX_PIN_BIT;
for (i, w) in tx_ring_mem.iter_mut().enumerate() {
*w = if (i & 1) == 0 { 0 } else { pin_mask };
}
// Create and start the TX DMA ring in main.
// let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
@@ -78,6 +66,7 @@ async fn main(spawner: Spawner) {
// Start DMA
tx_ring.start();
info!("TX DMA ring started");
dump_dma_ch0_regs();
let mut frame_buf = [0u32; 4096];
@@ -86,16 +75,25 @@ async fn main(spawner: Spawner) {
Timer::after(Duration::from_millis(400)).await;
info!("tick end");
let used = encode_uart_frames(TX_PIN_BIT, b"Hello marshmallow\r\n", &mut frame_buf).await;
// PHASE 1A (safest to validate hardware first): do nothing here; the DMA already
// streams the primed toggle pattern in tx_ring_mem. You should see PA2 toggling.
// Uncomment PHASE 1B below once you confirm toggling on a scope/LED.
// Wait for DMA to free space, async style
wait_for_space(&mut tx_ring, used / 2).await;
if let Err(e) = tx_ring.write_exact(&frame_buf[..used]).await {
warn!("DMA ring write error: {:?}", e);
// PHASE 1B: actively queue new data (only after confirming DMA advances).
let used = 256.min(frame_buf.len());
for i in 0..used { frame_buf[i] = if (i & 1) == 0 { 0 } else { pin_mask }; }
info!("a");
let free = tx_ring.capacity() - tx_ring.len().unwrap_or(0);
if free >= used {
if let Err(e) = tx_ring.write_exact(&frame_buf[..used]).await {
warn!("DMA ring write error: {:?}", e);
} else {
info!("Frame queued to DMA ring (free={})", free);
}
} else {
info!("Frame queued to DMA ring");
warn!("Skipping write (free={}, need={})", free, used);
}
info!("b");
yield_now().await;
}

4
dma_gpio2/src/config.rs
View File

@@ -4,9 +4,9 @@ use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
pub const BAUD: u32 = 9_600;
pub const TX_PIN_BIT: u8 = 2; // PA2
pub const TX_OVERSAMPLE: u16 = 1;
pub const RX_OVERSAMPLE: u16 = 16;
pub const RX_OVERSAMPLE: u16 = 1;
pub const RX_RING_BYTES: usize = 4096;
pub const TX_RING_BYTES: usize = 4096;
pub const TX_RING_BYTES: usize = 256;
pub const PIPE_RX_SIZE: usize = 256;
pub const UART_CFG: UartConfig = UartConfig {