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Priec
204
semestralka_1_connected/src/software_uart/uart_emulation.rs
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204
semestralka_1_connected/src/software_uart/uart_emulation.rs
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// src/software_uart/uart_emulation.rs
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use heapless::Vec;
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum Parity {
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None,
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Even,
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Odd,
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}
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum StopBits {
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One,
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Two,
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}
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#[derive(Clone, Copy, Debug)]
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pub struct UartConfig {
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pub data_bits: u8,
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pub parity: Parity,
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pub stop_bits: StopBits,
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}
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impl Default for UartConfig {
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fn default() -> Self {
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Self {
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data_bits: 8,
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parity: Parity::None,
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stop_bits: StopBits::One,
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}
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}
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}
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/// Encodes one byte into a sequence of GPIO BSRR words
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pub fn encode_uart_byte_cfg(
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pin_bit: u8,
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data: u8,
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cfg: &UartConfig,
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out: &mut [u32; 12],
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) -> usize {
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// GPIOx_BSRR register str. 636 kap. 13.4.7
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let set_high = |bit: u8| -> u32 { 1u32 << bit };
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// let set_low = |bit: u8| -> u32 { 0 }; // ODR
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let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
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let mut idx = 0usize;
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// START bit (LOW)
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out[idx] = set_low(pin_bit);
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idx += 1;
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// Data bits, LSB-first
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let nbits = cfg.data_bits.clamp(5, 8);
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for i in 0..nbits {
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let one = ((data >> i) & 1) != 0;
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out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
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idx += 1;
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}
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// Parity
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match cfg.parity {
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Parity::None => {}
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Parity::Even | Parity::Odd => {
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let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
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let ones = (data & mask).count_ones() & 1;
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let par_bit_is_one = match cfg.parity {
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Parity::Even => ones == 1,
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Parity::Odd => ones == 0,
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_ => false,
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};
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out[idx] = if par_bit_is_one {
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set_high(pin_bit)
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} else {
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set_low(pin_bit)
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};
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idx += 1;
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}
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}
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// STOP bits (HIGH)
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let stop_ticks = match cfg.stop_bits {
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StopBits::One => 1usize,
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StopBits::Two => 2usize,
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};
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for _ in 0..stop_ticks {
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out[idx] = set_high(pin_bit);
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idx += 1;
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}
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idx
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}
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/// Decode an oversampled stream of logic levels into UART bytes.
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/// Returns (decoded bytes, number of samples consumed/processed).
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pub fn decode_uart_samples(
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samples: &[u8],
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oversample: u16,
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cfg: &UartConfig,
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) -> (heapless::Vec<u8, 256>, usize) {
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let mut out = Vec::<u8, 256>::new();
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let mut idx = 0usize;
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let nbits = cfg.data_bits as usize;
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let ovs = oversample as usize;
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// Calculate total frame width in samples to ensure we have enough data
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// 1 start + n data + parity? + stops
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let parity_bits = match cfg.parity {
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Parity::None => 0,
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_ => 1,
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};
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let stop_bits_count = match cfg.stop_bits {
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StopBits::One => 1,
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StopBits::Two => 2,
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};
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let frame_bits = 1 + nbits + parity_bits + stop_bits_count;
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let frame_len = frame_bits * ovs;
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// Helper: Majority vote over 3 samples centered at `i`
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let get_bit = |i: usize| -> u8 {
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let mut votes = 0;
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// Check i-1, i, i+1. Saturating sub/add handles boundaries roughly.
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if i > 0 && samples.get(i - 1).map_or(true, |&x| x != 0) {
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votes += 1;
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}
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if samples.get(i).map_or(true, |&x| x != 0) {
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votes += 1;
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}
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if samples.get(i + 1).map_or(true, |&x| x != 0) {
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votes += 1;
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}
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if votes >= 2 {
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1
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} else {
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0
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}
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};
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// We loop while we have enough remaining samples for a full frame
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while idx + frame_len <= samples.len() {
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// Wait for falling edge (High -> Low)
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// samples[idx] == 1 (Idle/Stop) && samples[idx+1] == 0 (Start)
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if samples[idx] != 0 && samples[idx + 1] == 0 {
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// Align to center of START bit
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// Start bit begins at idx+1. Center is at idx + 1 + (ovs/2)
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let center_offset = 1 + (ovs / 2);
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let mut scan_idx = idx + center_offset;
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// 1. Validate Start Bit (Must be 0)
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if get_bit(scan_idx) != 0 {
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idx += 1; // False start (noise), move on
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continue;
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}
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// Move to center of first data bit
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scan_idx += ovs;
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// 2. Read Data Bits
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let mut data: u8 = 0;
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for bit in 0..nbits {
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if get_bit(scan_idx) == 1 {
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data |= 1 << bit;
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}
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scan_idx += ovs;
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}
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// 3. Skip Parity (if any)
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if cfg.parity != Parity::None {
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scan_idx += ovs;
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}
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// 4. Validate Stop Bit (Must be 1)
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// If stop bit is 0, it's a framing error. We reject the whole byte.
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if get_bit(scan_idx) == 0 {
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idx += 1; // Try to find a real start bit on the next sample
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continue;
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}
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// 5. Byte is valid
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let _ = out.push(data);
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// 6. Active Resync: Fast-forward through the stop bit(s) and idle time
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// scan_idx is currently at the center of the Stop bit.
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idx = scan_idx;
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// Advance while we are reading High (1).
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// As soon as we see Low (0), we stop. That 0 is the beginning of the NEXT start bit.
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// The outer loop expects `idx` to be the High *before* the start bit, so we will handle that.
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while idx < samples.len() && samples[idx] != 0 {
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idx += 1;
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}
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// Back up one step.
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// The outer loop logic is: `if samples[idx] != 0 && samples[idx+1] == 0`.
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// If we stopped at `idx` because it was 0, then `idx-1` was the last 1 (Idle).
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if idx > 0 {
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idx -= 1;
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}
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} else {
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// No start bit detected here, move to next sample
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idx += 1;
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}
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}
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(out, idx)
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}
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