time to do final merge
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Priec
195
semestralka_1_connected/src/bin/main.rs
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195
semestralka_1_connected/src/bin/main.rs
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// src/bin/main.rs
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#![no_std]
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#![no_main]
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use defmt::*;
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use embassy_executor::Spawner;
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use embassy_time::Instant;
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use embassy_stm32::dma::Request;
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use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
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use dma_gpio::software_uart::{
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dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
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gpio_dma_uart_rx::rx_dma_task,
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debug::dump_tim6_regs,
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};
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use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
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use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES};
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use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
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use static_cell::StaticCell;
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use embassy_futures::yield_now;
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use dma_gpio::hw_uart_pc::usart1;
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use dma_gpio::hw_uart_pc::driver::uart_task;
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use embassy_stm32::usart::{BufferedUart, Config, BufferedInterruptHandler};
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use embassy_stm32::peripherals;
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use embassy_stm32::bind_interrupts;
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use embassy_stm32::Config as CPUConfig;
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use dma_gpio::config::{PIPE_HW_TX, PIPE_HW_RX, PIPE_SW_TX, PIPE_SW_RX};
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use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
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use dma_gpio::hw_uart_internal::usart2;
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use dma_gpio::hw_uart_internal::driver::uart_task as uart_task_internal;
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use dma_gpio::software_uart::decode_uart_samples;
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use dma_gpio::config::UART_CFG;
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use dma_gpio::config::{PIPE_INT_TX, PIPE_INT_RX};
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use embassy_time::{Duration, Timer};
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use embassy_stm32::pac;
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use embassy_stm32::interrupt;
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use {defmt_rtt as _, panic_probe as _};
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use embassy_stm32::{
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rcc::{self, Pll, PllSource},
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};
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use embassy_stm32::rcc::PllMul;
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use embassy_stm32::rcc::PllDiv;
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use embassy_stm32::rcc::PllPreDiv;
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use embassy_stm32::rcc::Sysclk;
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use cortex_m::interrupt::Mutex;
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use core::cell::RefCell;
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use embassy_sync::channel::Channel;
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static PD6_BITS: Channel<CriticalSectionRawMutex, u8, 16384> = Channel::new();
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bind_interrupts!(struct Irqs {
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USART1 => BufferedInterruptHandler<peripherals::USART1>;
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});
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bind_interrupts!(struct Irqs2 {
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USART2 => BufferedInterruptHandler<peripherals::USART2>;
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});
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// Software uart
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pub const TIM6_UP_REQ: Request = 4;
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static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
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static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
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static mut RX_PIN: Option<Input<'static>> = None;
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#[embassy_executor::main]
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async fn main(spawner: Spawner) {
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info!("boot");
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let mut config = CPUConfig::default();
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config.rcc.hsi = true;
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config.rcc.sys = Sysclk::PLL1_R;
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config.rcc.pll1 = Some(Pll {
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source: PllSource::HSI,
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// 16 MHz / 1 × 20 / 2 = 160 MHz
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prediv: PllPreDiv::DIV1, // or 1.into()
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mul: PllMul::MUL20, // or 20.into()
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divp: None,
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divq: None,
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divr: Some(PllDiv::DIV2), // or Some(2.into())
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});
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config.enable_independent_io_supply = true;
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config.enable_independent_analog_supply = true;
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let p = embassy_stm32::init(config);
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let f_tim7 = rcc::frequency::<embassy_stm32::peripherals::TIM7>().0;
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info!("TIM7 clock after PLL config = {} Hz", f_tim7);
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// HARDWARE UART to the PC
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let mut cfg = Config::default();
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cfg.baudrate = BAUD;
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static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
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static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
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let uart = BufferedUart::new(
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p.USART1,
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p.PA10, // RX pin
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p.PA9, // TX pin
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TX_BUF.init([0; 256]),
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RX_BUF.init([0; 256]),
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Irqs,
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cfg,
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).unwrap();
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let yield_period = usart1::setup_and_spawn(BAUD);
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spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
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// END OF HARDWARE UART to the PC
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// INTERNAL HARDWARE UART (USART2)
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let mut cfg2 = Config::default();
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cfg2.baudrate = BAUD;
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static TX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
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static RX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
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let uart2 = BufferedUart::new(
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p.USART2,
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p.PA3, // RX
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p.PA2, // TX
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TX_BUF2.init([0; 256]),
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RX_BUF2.init([0; 256]),
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Irqs2,
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cfg2,
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).unwrap();
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let _ = usart2::setup_and_spawn(BAUD);
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spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
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info!("USART2 ready");
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// END OF INTERNAL HARDWARE UART (USART2)
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// USART1 <-> USART2 bridge
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spawner.spawn(bridge_usart1_rx_to_usart2_tx(&PIPE_HW_RX, &PIPE_INT_TX).unwrap());
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spawner.spawn(bridge_usart2_rx_to_usart1_tx(&PIPE_INT_RX, &PIPE_HW_TX).unwrap());
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info!("USART1 <-> USART2 bridge active");
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// END OF USART1 <-> USART2 bridge
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// SOFTWARE UART
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// let _rx = Input::new(p.PD6, Pull::Up);
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let rx_pin = Input::new(p.PD6, Pull::Up);
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unsafe { RX_PIN = Some(rx_pin) };
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// Configure TX as output (PB0)
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let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
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init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
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init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
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dump_tim6_regs();
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// EDN OF SOFTWARE UART
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// Allocate DMA RX ring buffer
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let rx_ring = SW_RX_RING.init([0u8; RX_RING_BYTES]);
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// Pointer to GPIOD Input Data Register (IDR)
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let gpio_idr = embassy_stm32::pac::GPIOD.idr().as_ptr() as *mut u8;
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// Spawn software UART RX DMA task
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spawner.spawn(rx_dma_task(p.GPDMA1_CH1, gpio_idr, rx_ring, &PIPE_SW_RX).unwrap());
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info!("SW UART RX DMA started");
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// Process decoded bytes coming from PIPE_SW_RX
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let mut buf = [0u8; 64];
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loop {
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let n = PIPE_SW_RX.read(&mut buf).await;
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if n > 0 {
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info!("SW UART decoded: {:a}", &buf[..n]);
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}
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yield_now().await;
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}
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}
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#[embassy_executor::task]
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pub async fn bridge_usart1_rx_to_usart2_tx(
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usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
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usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
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) {
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let mut buf = [0u8; 64];
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loop {
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let n = usart1_rx.read(&mut buf).await;
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if n > 0 {
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let _ = usart2_tx.write(&buf[..n]).await;
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// info!("bridge USART1 - USART2 sent:{} bytes: {}", n, &buf[..n]);
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}
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yield_now().await;
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}
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}
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#[embassy_executor::task]
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pub async fn bridge_usart2_rx_to_usart1_tx(
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usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
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usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
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) {
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let mut buf = [0u8; 64];
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loop {
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let n = usart2_rx.read(&mut buf).await;
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if n > 0 {
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let _ = usart1_tx.write(&buf[..n]).await;
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// info!("bridge: USART2 -> USART1 sent {} bytes", n);
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}
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yield_now().await;
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}
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}
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