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semestralka_1/src/bin/main.rs

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+// src/bin/main.rs
+#![no_std]
+#![no_main]
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::bind_interrupts;
+use embassy_stm32::peripherals;
+use embassy_stm32::usart::{BufferedInterruptHandler, BufferedUart, Config};
+use embedded_io_async::{Read, Write};
+use embassy_time::{Timer, Duration, Instant};
+use static_cell::StaticCell;
+use embassy_futures::yield_now;
+use {defmt_rtt as _, panic_probe as _};
+use embassy_futures::select::{select, Either};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use async_uart::safety::{preflight_and_suggest_yield_period, RX_PIPE_CAP, TX_PIPE_CAP};
+
+static UART_TX: Pipe<CriticalSectionRawMutex, TX_PIPE_CAP> = Pipe::new();
+static UART_RX: Pipe<CriticalSectionRawMutex, RX_PIPE_CAP> = Pipe::new();
+
+bind_interrupts!(
+    struct Irqs {
+        USART1 => BufferedInterruptHandler<peripherals::USART1>;
+    }
+);
+
+#[embassy_executor::task]
+async fn uart_task(mut uart: BufferedUart<'static>) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+    loop {
+        // Wait for either RX or TX events.
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            // Until there's outgoing data in TX pipe
+            let n = UART_TX.read(&mut tx_buf).await;
+            n
+        };
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    // Forward to RX pipe
+                    let _ = UART_RX.write(&rx_byte).await;
+                    let _ = UART_TX.try_write(&rx_byte);
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+    }
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("tititititi");
+    let p = embassy_stm32::init(Default::default());
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let tx_buf = TX_BUF.init([0; 256]);
+    let rx_buf = RX_BUF.init([0; 256]);
+    let mut cfg = Config::default();
+    cfg.baudrate = 230_400;
+
+    // Call preflight and get the computed yield period
+    let yield_period = preflight_and_suggest_yield_period(cfg.baudrate);
+
+    let usart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX
+        p.PA9,  // TX
+        tx_buf,
+        rx_buf,
+        Irqs,
+        cfg,
+    ).unwrap();
+    info!("starting uart task");
+    spawner.spawn(uart_task(usart)).unwrap();
+
+    let mut counter: u32 = 0;
+    let mut rx_buf = [0u8; 64];
+    let mut last_yield = Instant::now();
+
+    loop {
+        counter = counter.wrapping_add(1);
+        // Poll RX pipe for new data (non-blocking)
+        if let Ok(n) = UART_RX.try_read(&mut rx_buf) {
+            if n > 0 {
+                if let Ok(s) = core::str::from_utf8(&rx_buf[..n]) {
+                    info!("RX got: {}", s);
+                } else {
+                    info!("RX got (non‑utf8): {:?}", &rx_buf[..n]);
+                }
+            }
+        }
+
+        // Guaranteed to yield before ISR RX buffer can overflow
+        if Instant::now().duration_since(last_yield) >= yield_period {
+            yield_now().await;
+            last_yield = Instant::now();
+            // info!("Yield mf {}", counter);
+        }
+        // Timer::after(Duration::from_micros(1)).await;
+        // Timer::after(Duration::from_secs(5)).await;
+    }
+}